[AMDGPU] Add unfold test.

Author: harrisonGPU

llvm/lib/Target/AMDGPU/SIISelLowering.cpp

@@ -17565,7 +17565,7 @@ SITargetLowering::lowerIdempotentRMWIntoFencedLoad(AtomicRMWInst *AI) const {
 bool SITargetLowering::hasAndNot(SDValue Op) const {
   // Return false if the operation is divergent, as AND-NOT is a scalar-only
   // instruction.
-  if (Op->isDivergent() || !Op->isMachineOpcode())
+  if (Op->isDivergent())
     return false;
 
   EVT VT = Op.getValueType();

llvm/test/CodeGen/AMDGPU/andorn2.ll

@@ -25,24 +25,6 @@ entry:
   ret void
 }
 
-; GCN-LABEL: {{^}}scalar_andn2_i32_one_sgpr
-; GCN: s_andn2_b32
-define i32 @scalar_andn2_i32_one_sgpr(i32 inreg %a, i32 inreg %b) {
-entry:
-  %nb = xor i32 %b, -1
-  %and = and i32 %a, %nb
-  ret i32 %and
-}
-
-; GCN-LABEL: {{^}}scalar_andn2_i64_one_sgpr
-; GCN: s_andn2_b64
-define i64 @scalar_andn2_i64_one_sgpr(i64 inreg %a, i64 inreg %b) {
-entry:
-  %nb = xor i64 %b, -1
-  %and = and i64 %a, %nb
-  ret i64 %and
-}
-
 ; GCN-LABEL: {{^}}scalar_orn2_i32_one_use
 ; GCN: s_orn2_b32
 define amdgpu_kernel void @scalar_orn2_i32_one_use(
@@ -65,24 +47,6 @@ entry:
   ret void
 }
 
-; GCN-LABEL: {{^}}scalar_orn2_i32_one_use_sgpr
-; GCN: s_orn2_b32
-define i32 @scalar_orn2_i32_one_use_sgpr(i32 inreg %a, i32 inreg %b) {
-entry:
-  %nb = xor i32 %b, -1
-  %or = or i32 %a, %nb
-  ret i32 %or;
-}
-
-; GCN-LABEL: {{^}}scalar_orn2_i64_one_use_sgpr
-; GCN: s_orn2_b64
-define i64 @scalar_orn2_i64_one_use_sgpr(i64 inreg %a, i64 inreg %b) {
-entry:
-  %nb = xor i64 %b, -1
-  %or = or i64 %a, %nb
-  ret i64 %or;
-}
-
 ; GCN-LABEL: {{^}}vector_andn2_i32_s_v_one_use
 ; GCN: v_not_b32
 ; GCN: v_and_b32