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[AMDGPU][MC] Avoid creating lit64() operands unless asked or needed. (#161191)
There should normally be no need to generate implicit lit64() modifiers on the assembler side. It's the encoder's responsibility to recognise literals that are implicitly 64 bits wide. The exceptions are where we rewrite floating-point operand values as integer ones, which would not be assembled back to the original values unless wrapped into lit64(). Respect explicit lit() modifiers for non-inline values as necessary to avoid regressions in MC tests. This change still doesn't prevent use of inline constants where lit()/lit64 is specified; subject to a separate patch. On disassembling, only create lit64() operands where necessary for correct round-tripping. Add round-tripping tests where useful and feasible.
1 parent 301ecc6 commit 20f41ed

24 files changed

+428
-387
lines changed

‎llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp‎

Lines changed: 47 additions & 25 deletions
Original file line numberDiff line numberDiff line change
@@ -2339,6 +2339,7 @@ void AMDGPUOperand::addLiteralImmOperand(MCInst &Inst, int64_t Val, bool ApplyMo
23392339
bool CanUse64BitLiterals =
23402340
AsmParser->has64BitLiterals() &&
23412341
!(InstDesc.TSFlags & (SIInstrFlags::VOP3 | SIInstrFlags::VOP3P));
2342+
LitModifier Lit = getModifiers().Lit;
23422343
MCContext &Ctx = AsmParser->getContext();
23432344

23442345
if (Imm.IsFPImm) { // We got fp literal token
@@ -2372,10 +2373,23 @@ void AMDGPUOperand::addLiteralImmOperand(MCInst &Inst, int64_t Val, bool ApplyMo
23722373

23732374
if ((OpTy == AMDGPU::OPERAND_REG_IMM_FP64 ||
23742375
OpTy == AMDGPU::OPERAND_REG_INLINE_C_FP64 ||
2375-
OpTy == AMDGPU::OPERAND_REG_INLINE_AC_FP64) &&
2376-
CanUse64BitLiterals && Lo_32(Val) != 0) {
2377-
Inst.addOperand(MCOperand::createExpr(
2378-
AMDGPUMCExpr::createLit(LitModifier::Lit64, Val, Ctx)));
2376+
OpTy == AMDGPU::OPERAND_REG_INLINE_AC_FP64)) {
2377+
if (CanUse64BitLiterals && Lit == LitModifier::None &&
2378+
(isInt<32>(Val) || isUInt<32>(Val))) {
2379+
// The floating-point operand will be verbalized as an
2380+
// integer one. If that integer happens to fit 32 bits, on
2381+
// re-assembling it will be intepreted as the high half of
2382+
// the actual value, so we have to wrap it into lit64().
2383+
Lit = LitModifier::Lit64;
2384+
} else if (Lit == LitModifier::Lit) {
2385+
// For FP64 operands lit() specifies the high half of the value.
2386+
Val = Hi_32(Val);
2387+
}
2388+
}
2389+
2390+
if (Lit != LitModifier::None) {
2391+
Inst.addOperand(
2392+
MCOperand::createExpr(AMDGPUMCExpr::createLit(Lit, Val, Ctx)));
23792393
} else {
23802394
Inst.addOperand(MCOperand::createImm(Val));
23812395
}
@@ -2388,9 +2402,13 @@ void AMDGPUOperand::addLiteralImmOperand(MCInst &Inst, int64_t Val, bool ApplyMo
23882402
llvm_unreachable("fp literal in 64-bit integer instruction.");
23892403

23902404
case AMDGPU::OPERAND_KIMM64:
2391-
if (CanUse64BitLiterals && Lo_32(Val) != 0) {
2392-
Inst.addOperand(MCOperand::createExpr(
2393-
AMDGPUMCExpr::createLit(LitModifier::Lit64, Val, Ctx)));
2405+
if (CanUse64BitLiterals && Lit == LitModifier::None &&
2406+
(isInt<32>(Val) || isUInt<32>(Val)))
2407+
Lit = LitModifier::Lit64;
2408+
2409+
if (Lit != LitModifier::None) {
2410+
Inst.addOperand(
2411+
MCOperand::createExpr(AMDGPUMCExpr::createLit(Lit, Val, Ctx)));
23942412
} else {
23952413
Inst.addOperand(MCOperand::createImm(Val));
23962414
}
@@ -2479,13 +2497,12 @@ void AMDGPUOperand::addLiteralImmOperand(MCInst &Inst, int64_t Val, bool ApplyMo
24792497
// truncated to uint32_t), if the target doesn't support 64-bit literals, or
24802498
// the lit modifier is explicitly used, we need to truncate it to the 32
24812499
// LSBs.
2482-
if (!AsmParser->has64BitLiterals() ||
2483-
getModifiers().Lit == LitModifier::Lit)
2500+
if (!AsmParser->has64BitLiterals() || Lit == LitModifier::Lit)
24842501
Val = Lo_32(Val);
24852502

2486-
if (CanUse64BitLiterals && (!isInt<32>(Val) || !isUInt<32>(Val))) {
2487-
Inst.addOperand(MCOperand::createExpr(
2488-
AMDGPUMCExpr::createLit(LitModifier::Lit64, Val, Ctx)));
2503+
if (Lit != LitModifier::None) {
2504+
Inst.addOperand(
2505+
MCOperand::createExpr(AMDGPUMCExpr::createLit(Lit, Val, Ctx)));
24892506
} else {
24902507
Inst.addOperand(MCOperand::createImm(Val));
24912508
}
@@ -2509,15 +2526,18 @@ void AMDGPUOperand::addLiteralImmOperand(MCInst &Inst, int64_t Val, bool ApplyMo
25092526
// 1) explicitly forced by using lit modifier;
25102527
// 2) the value is a valid 32-bit representation (signed or unsigned),
25112528
// meanwhile not forced by lit64 modifier.
2512-
if (getModifiers().Lit == LitModifier::Lit ||
2513-
(getModifiers().Lit != LitModifier::Lit64 &&
2514-
(isInt<32>(Val) || isUInt<32>(Val))))
2529+
if (Lit == LitModifier::Lit ||
2530+
(Lit != LitModifier::Lit64 && (isInt<32>(Val) || isUInt<32>(Val))))
25152531
Val = static_cast<uint64_t>(Val) << 32;
25162532
}
25172533

2518-
if (CanUse64BitLiterals && Lo_32(Val) != 0) {
2519-
Inst.addOperand(MCOperand::createExpr(
2520-
AMDGPUMCExpr::createLit(LitModifier::Lit64, Val, Ctx)));
2534+
// For FP64 operands lit() specifies the high half of the value.
2535+
if (Lit == LitModifier::Lit)
2536+
Val = Hi_32(Val);
2537+
2538+
if (Lit != LitModifier::None) {
2539+
Inst.addOperand(
2540+
MCOperand::createExpr(AMDGPUMCExpr::createLit(Lit, Val, Ctx)));
25212541
} else {
25222542
Inst.addOperand(MCOperand::createImm(Val));
25232543
}
@@ -2538,13 +2558,12 @@ void AMDGPUOperand::addLiteralImmOperand(MCInst &Inst, int64_t Val, bool ApplyMo
25382558
return;
25392559

25402560
case AMDGPU::OPERAND_KIMM64:
2541-
if ((isInt<32>(Val) || isUInt<32>(Val)) &&
2542-
getModifiers().Lit != LitModifier::Lit64)
2561+
if ((isInt<32>(Val) || isUInt<32>(Val)) && Lit != LitModifier::Lit64)
25432562
Val <<= 32;
25442563

2545-
if (CanUse64BitLiterals && Lo_32(Val) != 0) {
2546-
Inst.addOperand(MCOperand::createExpr(
2547-
AMDGPUMCExpr::createLit(LitModifier::Lit64, Val, Ctx)));
2564+
if (Lit != LitModifier::None) {
2565+
Inst.addOperand(
2566+
MCOperand::createExpr(AMDGPUMCExpr::createLit(Lit, Val, Ctx)));
25482567
} else {
25492568
Inst.addOperand(MCOperand::createImm(Val));
25502569
}
@@ -4821,12 +4840,15 @@ bool AMDGPUAsmParser::validateSOPLiteral(const MCInst &Inst,
48214840
const MCOperand &MO = Inst.getOperand(OpIdx);
48224841
// Exclude special imm operands (like that used by s_set_gpr_idx_on)
48234842
if (AMDGPU::isSISrcOperand(Desc, OpIdx)) {
4843+
bool IsLit = false;
48244844
std::optional<int64_t> Imm;
48254845
if (MO.isImm()) {
48264846
Imm = MO.getImm();
48274847
} else if (MO.isExpr()) {
4828-
if (isLitExpr(MO.getExpr()))
4848+
if (isLitExpr(MO.getExpr())) {
4849+
IsLit = true;
48294850
Imm = getLitValue(MO.getExpr());
4851+
}
48304852
} else {
48314853
continue;
48324854
}
@@ -4836,7 +4858,7 @@ bool AMDGPUAsmParser::validateSOPLiteral(const MCInst &Inst,
48364858
} else if (!isInlineConstant(Inst, OpIdx)) {
48374859
auto OpType = static_cast<AMDGPU::OperandType>(
48384860
Desc.operands()[OpIdx].OperandType);
4839-
int64_t Value = encode32BitLiteral(*Imm, OpType);
4861+
int64_t Value = encode32BitLiteral(*Imm, OpType, IsLit);
48404862
if (NumLiterals == 0 || LiteralValue != Value) {
48414863
LiteralValue = Value;
48424864
++NumLiterals;

‎llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp‎

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -1551,7 +1551,7 @@ AMDGPUDisassembler::decodeMandatoryLiteral64Constant(uint64_t Val) const {
15511551
HasLiteral = true;
15521552
Literal = Literal64 = Val;
15531553

1554-
bool UseLit64 = Lo_32(Literal64) != 0;
1554+
bool UseLit64 = Hi_32(Literal64) == 0;
15551555
return UseLit64 ? MCOperand::createExpr(AMDGPUMCExpr::createLit(
15561556
LitModifier::Lit64, Literal64, getContext()))
15571557
: MCOperand::createImm(Literal64);
@@ -1584,11 +1584,11 @@ MCOperand AMDGPUDisassembler::decodeLiteralConstant(const MCInstrDesc &Desc,
15841584
if (CanUse64BitLiterals) {
15851585
if (OpDesc.OperandType == AMDGPU::OPERAND_REG_IMM_INT64 ||
15861586
OpDesc.OperandType == AMDGPU::OPERAND_REG_INLINE_C_INT64)
1587-
UseLit64 = !isInt<32>(Val) || !isUInt<32>(Val);
1587+
UseLit64 = false;
15881588
else if (OpDesc.OperandType == AMDGPU::OPERAND_REG_IMM_FP64 ||
15891589
OpDesc.OperandType == AMDGPU::OPERAND_REG_INLINE_C_FP64 ||
15901590
OpDesc.OperandType == AMDGPU::OPERAND_REG_INLINE_AC_FP64)
1591-
UseLit64 = Lo_32(Val) != 0;
1591+
UseLit64 = Hi_32(Literal64) == 0;
15921592
}
15931593

15941594
return UseLit64 ? MCOperand::createExpr(AMDGPUMCExpr::createLit(
@@ -1614,12 +1614,12 @@ AMDGPUDisassembler::decodeLiteral64Constant(const MCInst &Inst) const {
16141614
const MCOperandInfo &OpDesc = Desc.operands()[Inst.getNumOperands()];
16151615
if (OpDesc.OperandType == AMDGPU::OPERAND_REG_IMM_INT64 ||
16161616
OpDesc.OperandType == AMDGPU::OPERAND_REG_INLINE_C_INT64) {
1617-
UseLit64 = !isInt<32>(Literal64) || !isUInt<32>(Literal64);
1617+
UseLit64 = false;
16181618
} else {
16191619
assert(OpDesc.OperandType == AMDGPU::OPERAND_REG_IMM_FP64 ||
16201620
OpDesc.OperandType == AMDGPU::OPERAND_REG_INLINE_C_FP64 ||
16211621
OpDesc.OperandType == AMDGPU::OPERAND_REG_INLINE_AC_FP64);
1622-
UseLit64 = Lo_32(Literal64) != 0;
1622+
UseLit64 = Hi_32(Literal64) == 0;
16231623
}
16241624

16251625
return UseLit64 ? MCOperand::createExpr(AMDGPUMCExpr::createLit(

‎llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUMCCodeEmitter.cpp‎

Lines changed: 6 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -452,13 +452,16 @@ void AMDGPUMCCodeEmitter::encodeInstruction(const MCInst &MI,
452452
// Yes! Encode it
453453
int64_t Imm = 0;
454454

455+
bool IsLit = false;
455456
if (Op.isImm())
456457
Imm = Op.getImm();
457458
else if (Op.isExpr()) {
458-
if (const auto *C = dyn_cast<MCConstantExpr>(Op.getExpr()))
459+
if (const auto *C = dyn_cast<MCConstantExpr>(Op.getExpr())) {
459460
Imm = C->getValue();
460-
else if (AMDGPU::isLitExpr(Op.getExpr()))
461+
} else if (AMDGPU::isLitExpr(Op.getExpr())) {
462+
IsLit = true;
461463
Imm = AMDGPU::getLitValue(Op.getExpr());
464+
}
462465
} else // Exprs will be replaced with a fixup value.
463466
llvm_unreachable("Must be immediate or expr");
464467

@@ -468,7 +471,7 @@ void AMDGPUMCCodeEmitter::encodeInstruction(const MCInst &MI,
468471
} else {
469472
auto OpType =
470473
static_cast<AMDGPU::OperandType>(Desc.operands()[i].OperandType);
471-
Imm = AMDGPU::encode32BitLiteral(Imm, OpType);
474+
Imm = AMDGPU::encode32BitLiteral(Imm, OpType, IsLit);
472475
support::endian::write<uint32_t>(CB, Imm, llvm::endianness::little);
473476
}
474477

‎llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.cpp‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -3145,7 +3145,7 @@ bool isValid32BitLiteral(uint64_t Val, bool IsFP64) {
31453145
return isUInt<32>(Val) || isInt<32>(Val);
31463146
}
31473147

3148-
int64_t encode32BitLiteral(int64_t Imm, OperandType Type) {
3148+
int64_t encode32BitLiteral(int64_t Imm, OperandType Type, bool IsLit) {
31493149
switch (Type) {
31503150
default:
31513151
break;
@@ -3168,7 +3168,7 @@ int64_t encode32BitLiteral(int64_t Imm, OperandType Type) {
31683168
case OPERAND_REG_INLINE_C_INT32:
31693169
return Lo_32(Imm);
31703170
case OPERAND_REG_IMM_FP64:
3171-
return Hi_32(Imm);
3171+
return IsLit ? Imm : Hi_32(Imm);
31723172
}
31733173
return Imm;
31743174
}

‎llvm/lib/Target/AMDGPU/Utils/AMDGPUBaseInfo.h‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1727,7 +1727,7 @@ LLVM_READNONE
17271727
bool isValid32BitLiteral(uint64_t Val, bool IsFP64);
17281728

17291729
LLVM_READNONE
1730-
int64_t encode32BitLiteral(int64_t Imm, OperandType Type);
1730+
int64_t encode32BitLiteral(int64_t Imm, OperandType Type, bool IsLit);
17311731

17321732
bool isArgPassedInSGPR(const Argument *Arg);
17331733

‎llvm/test/MC/AMDGPU/gfx1250_asm_salu_lit64.s‎

Lines changed: 28 additions & 22 deletions
Original file line numberDiff line numberDiff line change
@@ -1,64 +1,70 @@
1-
// RUN: llvm-mc -triple=amdgcn -show-encoding -mcpu=gfx1250 %s | FileCheck --check-prefix=GFX1250 %s
1+
// NOTE: Assertions have been autogenerated by utils/update_mc_test_checks.py UTC_ARGS: --version 5
2+
// RUN: llvm-mc -triple=amdgcn -show-encoding -mcpu=gfx1250 %s | FileCheck --check-prefixes=GFX1250,GFX1250-ASM %s
3+
// RUN: llvm-mc -triple=amdgcn -mcpu=gfx1250 -show-encoding %s | %extract-encodings | llvm-mc -triple=amdgcn -mcpu=gfx1250 -disassemble -show-encoding | FileCheck --check-prefixes=GFX1250,GFX1250-DIS %s
24

35
s_mov_b64 s[2:3], 0x10abcdef12345678
4-
// GFX1250: s_mov_b64 s[2:3], lit64(0x10abcdef12345678) ; encoding: [0xfe,0x01,0x82,0xbe,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10]
6+
// GFX1250: s_mov_b64 s[2:3], 0x10abcdef12345678 ; encoding: [0xfe,0x01,0x82,0xbe,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10]
57

68
s_add_nc_u64 s[2:3], s[4:5], 0x10abcdef12345678
7-
// GFX1250: s_add_nc_u64 s[2:3], s[4:5], lit64(0x10abcdef12345678) ; encoding: [0x04,0xfe,0x82,0xa9,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10]
9+
// GFX1250: s_add_nc_u64 s[2:3], s[4:5], 0x10abcdef12345678 ; encoding: [0x04,0xfe,0x82,0xa9,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10]
810

911
s_mul_u64 s[2:3], 0x10abcdef12345678, s[4:5]
10-
// GFX1250: s_mul_u64 s[2:3], lit64(0x10abcdef12345678), s[4:5] ; encoding: [0xfe,0x04,0x82,0xaa,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10]
12+
// GFX1250: s_mul_u64 s[2:3], 0x10abcdef12345678, s[4:5] ; encoding: [0xfe,0x04,0x82,0xaa,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10]
1113

1214
s_and_b64 s[2:3], 0x10abcdef12345678, s[4:5]
13-
// GFX1250: s_and_b64 s[2:3], lit64(0x10abcdef12345678), s[4:5] ; encoding: [0xfe,0x04,0x82,0x8b,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10]
15+
// GFX1250: s_and_b64 s[2:3], 0x10abcdef12345678, s[4:5] ; encoding: [0xfe,0x04,0x82,0x8b,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10]
1416

1517
s_or_b64 s[2:3], s[4:5], 0x10abcdef12345678
16-
// GFX1250: s_or_b64 s[2:3], s[4:5], lit64(0x10abcdef12345678) ; encoding: [0x04,0xfe,0x82,0x8c,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10]
18+
// GFX1250: s_or_b64 s[2:3], s[4:5], 0x10abcdef12345678 ; encoding: [0x04,0xfe,0x82,0x8c,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10]
1719

1820
s_xor_b64 s[2:3], 0x10abcdef12345678, s[4:5]
19-
// GFX1250: s_xor_b64 s[2:3], lit64(0x10abcdef12345678), s[4:5] ; encoding: [0xfe,0x04,0x82,0x8d,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10]
21+
// GFX1250: s_xor_b64 s[2:3], 0x10abcdef12345678, s[4:5] ; encoding: [0xfe,0x04,0x82,0x8d,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10]
2022

2123
s_and_not1_b64 s[2:3], 0x10abcdef12345678, 0x10abcdef12345678
22-
// GFX1250: s_and_not1_b64 s[2:3], lit64(0x10abcdef12345678), lit64(0x10abcdef12345678) ; encoding: [0xfe,0xfe,0x82,0x91,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10]
24+
// GFX1250: s_and_not1_b64 s[2:3], 0x10abcdef12345678, 0x10abcdef12345678 ; encoding: [0xfe,0xfe,0x82,0x91,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10]
2325

2426
s_or_not1_b64 s[2:3], s[4:5], 0x10abcdef12345678
25-
// GFX1250: s_or_not1_b64 s[2:3], s[4:5], lit64(0x10abcdef12345678) ; encoding: [0x04,0xfe,0x82,0x92,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10]
27+
// GFX1250: s_or_not1_b64 s[2:3], s[4:5], 0x10abcdef12345678 ; encoding: [0x04,0xfe,0x82,0x92,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10]
2628

2729
s_andn2_b64 s[2:3], 0x10abcdef12345678, s[4:5]
28-
// GFX1250: s_and_not1_b64 s[2:3], lit64(0x10abcdef12345678), s[4:5] ; encoding: [0xfe,0x04,0x82,0x91,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10]
30+
// GFX1250: s_and_not1_b64 s[2:3], 0x10abcdef12345678, s[4:5] ; encoding: [0xfe,0x04,0x82,0x91,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10]
2931

3032
s_orn2_b64 s[2:3], s[4:5], 0x10abcdef12345678
31-
// GFX1250: s_or_not1_b64 s[2:3], s[4:5], lit64(0x10abcdef12345678) ; encoding: [0x04,0xfe,0x82,0x92,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10]
33+
// GFX1250: s_or_not1_b64 s[2:3], s[4:5], 0x10abcdef12345678 ; encoding: [0x04,0xfe,0x82,0x92,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10]
3234

3335
s_nand_b64 s[2:3], s[4:5], 0x10abcdef12345678
34-
// GFX1250: s_nand_b64 s[2:3], s[4:5], lit64(0x10abcdef12345678) ; encoding: [0x04,0xfe,0x82,0x8e,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10]
36+
// GFX1250: s_nand_b64 s[2:3], s[4:5], 0x10abcdef12345678 ; encoding: [0x04,0xfe,0x82,0x8e,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10]
3537

3638
s_nor_b64 s[2:3], s[4:5], 0x10abcdef12345678
37-
// GFX1250: s_nor_b64 s[2:3], s[4:5], lit64(0x10abcdef12345678) ; encoding: [0x04,0xfe,0x82,0x8f,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10]
39+
// GFX1250: s_nor_b64 s[2:3], s[4:5], 0x10abcdef12345678 ; encoding: [0x04,0xfe,0x82,0x8f,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10]
3840

3941
s_xnor_b64 s[2:3], s[4:5], 0x10abcdef12345678
40-
// GFX1250: s_xnor_b64 s[2:3], s[4:5], lit64(0x10abcdef12345678) ; encoding: [0x04,0xfe,0x82,0x90,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10]
42+
// GFX1250: s_xnor_b64 s[2:3], s[4:5], 0x10abcdef12345678 ; encoding: [0x04,0xfe,0x82,0x90,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10]
4143

4244
s_lshl_b64 s[2:3], 0x10abcdef12345678, s4
43-
// GFX1250: s_lshl_b64 s[2:3], lit64(0x10abcdef12345678), s4 ; encoding: [0xfe,0x04,0x82,0x84,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10]
45+
// GFX1250: s_lshl_b64 s[2:3], 0x10abcdef12345678, s4 ; encoding: [0xfe,0x04,0x82,0x84,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10]
4446

4547
s_lshr_b64 s[2:3], 0x10abcdef12345678, s4
46-
// GFX1250: s_lshr_b64 s[2:3], lit64(0x10abcdef12345678), s4 ; encoding: [0xfe,0x04,0x82,0x85,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10]
48+
// GFX1250: s_lshr_b64 s[2:3], 0x10abcdef12345678, s4 ; encoding: [0xfe,0x04,0x82,0x85,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10]
4749

4850
s_ashr_i64 s[2:3], 0x10abcdef12345678, s4
49-
// GFX1250: s_ashr_i64 s[2:3], lit64(0x10abcdef12345678), s4 ; encoding: [0xfe,0x04,0x82,0x86,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10]
51+
// GFX1250: s_ashr_i64 s[2:3], 0x10abcdef12345678, s4 ; encoding: [0xfe,0x04,0x82,0x86,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10]
5052

5153
s_bfe_u64 s[2:3], 0x10abcdef12345678, 5
52-
// GFX1250: s_bfe_u64 s[2:3], lit64(0x10abcdef12345678), 5 ; encoding: [0xfe,0x85,0x02,0x94,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10]
54+
// GFX1250: s_bfe_u64 s[2:3], 0x10abcdef12345678, 5 ; encoding: [0xfe,0x85,0x02,0x94,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10]
5355

5456
s_bfe_i64 s[2:3], 0x80abcdef12345678, 5
55-
// GFX1250: s_bfe_i64 s[2:3], lit64(0x80abcdef12345678), 5 ; encoding: [0xfe,0x85,0x82,0x94,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x80]
57+
// GFX1250: s_bfe_i64 s[2:3], 0x80abcdef12345678, 5 ; encoding: [0xfe,0x85,0x82,0x94,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x80]
5658

5759
s_cselect_b64 s[2:3], s[4:5], 0x10abcdef12345678
58-
// GFX1250: s_cselect_b64 s[2:3], s[4:5], lit64(0x10abcdef12345678) ; encoding: [0x04,0xfe,0x82,0x98,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10]
60+
// GFX1250: s_cselect_b64 s[2:3], s[4:5], 0x10abcdef12345678 ; encoding: [0x04,0xfe,0x82,0x98,0x78,0x56,0x34,0x12,0xef,0xcd,0xab,0x10]
5961

6062
s_mov_b64 s[2:3], 0xffffffff01234567
61-
// GFX1250: s_mov_b64 s[2:3], lit64(0xffffffff01234567) ; encoding: [0xfe,0x01,0x82,0xbe,0x67,0x45,0x23,0x01,0xff,0xff,0xff,0xff]
63+
// GFX1250: s_mov_b64 s[2:3], 0xffffffff01234567 ; encoding: [0xfe,0x01,0x82,0xbe,0x67,0x45,0x23,0x01,0xff,0xff,0xff,0xff]
6264

6365
s_mov_b64 s[2:3], lit64(0x777)
64-
// GFX1250: s_mov_b64 s[2:3], 0x777 ; encoding: [0xff,0x01,0x82,0xbe,0x77,0x07,0x00,0x00]
66+
// GFX1250-ASM: s_mov_b64 s[2:3], lit64(0x777) ; encoding: [0xff,0x01,0x82,0xbe,0x77,0x07,0x00,0x00]
67+
// GFX1250-DIS: s_mov_b64 s[2:3], 0x777 ; encoding: [0xff,0x01,0x82,0xbe,0x77,0x07,0x00,0x00]
68+
69+
s_mov_b64 s[2:3], 0x777
70+
// GFX1250: s_mov_b64 s[2:3], 0x777 ; encoding: [0xff,0x01,0x82,0xbe,0x77,0x07,0x00,0x00]

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