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Update tests
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‎llvm/test/CodeGen/AMDGPU/limit-coalesce.mir‎

Lines changed: 7 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -2,13 +2,13 @@
22

33
# Check that coalescer does not create wider register tuple than in source
44

5-
# CHECK: - { id: 2, class: vreg_64, preferred-register: '' }
6-
# CHECK: - { id: 3, class: vreg_64, preferred-register: '' }
7-
# CHECK: - { id: 4, class: vreg_64, preferred-register: '' }
8-
# CHECK: - { id: 5, class: vreg_96, preferred-register: '' }
9-
# CHECK: - { id: 6, class: vreg_96, preferred-register: '' }
10-
# CHECK: - { id: 7, class: vreg_128, preferred-register: '' }
11-
# CHECK: - { id: 8, class: vreg_128, preferred-register: '' }
5+
# CHECK: - { id: 2, class: vreg_64, preferred-register: '', flags: [ ] }
6+
# CHECK: - { id: 3, class: vreg_64, preferred-register: '', flags: [ ] }
7+
# CHECK: - { id: 4, class: vreg_64, preferred-register: '', flags: [ ] }
8+
# CHECK: - { id: 5, class: vreg_96, preferred-register: '', flags: [ ] }
9+
# CHECK: - { id: 6, class: vreg_96, preferred-register: '', flags: [ ] }
10+
# CHECK: - { id: 7, class: vreg_128, preferred-register: '', flags: [ ] }
11+
# CHECK: - { id: 8, class: vreg_128, preferred-register: '', flags: [ ] }
1212
# No more registers shall be defined
1313
# CHECK-NEXT: liveins:
1414
# CHECK: FLAT_STORE_DWORDX2 $vgpr0_vgpr1, %4,

‎llvm/test/CodeGen/MIR/X86/expected-named-register-in-allocation-hint.mir‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -14,8 +14,8 @@ name: test
1414
tracksRegLiveness: true
1515
registers:
1616
- { id: 0, class: gr32 }
17-
# CHECK: - { id: 1, class: gr32, preferred-register: '%0' }
18-
# CHECK: - { id: 2, class: gr32, preferred-register: '$edi' }
17+
# CHECK: - { id: 1, class: gr32, preferred-register: '%0', flags: [ ] }
18+
# CHECK: - { id: 2, class: gr32, preferred-register: '$edi', flags: [ ] }
1919
- { id: 1, class: gr32, preferred-register: '%0' }
2020
- { id: 2, class: gr32, preferred-register: '$edi' }
2121
body: |

‎llvm/test/CodeGen/MIR/X86/generic-instr-type.mir‎

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -18,11 +18,11 @@
1818
---
1919
name: test_vregs
2020
# CHECK: registers:
21-
# CHECK-NEXT: - { id: 0, class: _, preferred-register: '' }
22-
# CHECK-NEXT: - { id: 1, class: _, preferred-register: '' }
23-
# CHECK-NEXT: - { id: 2, class: _, preferred-register: '' }
24-
# CHECK-NEXT: - { id: 3, class: _, preferred-register: '' }
25-
# CHECK-NEXT: - { id: 4, class: _, preferred-register: '' }
21+
# CHECK-NEXT: - { id: 0, class: _, preferred-register: '', flags: [ ] }
22+
# CHECK-NEXT: - { id: 1, class: _, preferred-register: '', flags: [ ] }
23+
# CHECK-NEXT: - { id: 2, class: _, preferred-register: '', flags: [ ] }
24+
# CHECK-NEXT: - { id: 3, class: _, preferred-register: '', flags: [ ] }
25+
# CHECK-NEXT: - { id: 4, class: _, preferred-register: '', flags: [ ] }
2626
registers:
2727
- { id: 0, class: _ }
2828
- { id: 1, class: _ }

‎llvm/test/CodeGen/MIR/X86/register-operand-class.mir‎

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -6,11 +6,11 @@
66
---
77
# CHECK-LABEL: name: func
88
# CHECK: registers:
9-
# CHECK: - { id: 0, class: gr32, preferred-register: '' }
10-
# CHECK: - { id: 1, class: gr64, preferred-register: '' }
11-
# CHECK: - { id: 2, class: gr32, preferred-register: '' }
12-
# CHECK: - { id: 3, class: gr16, preferred-register: '' }
13-
# CHECK: - { id: 4, class: _, preferred-register: '' }
9+
# CHECK: - { id: 0, class: gr32, preferred-register: '', flags: [ ] }
10+
# CHECK: - { id: 1, class: gr64, preferred-register: '', flags: [ ] }
11+
# CHECK: - { id: 2, class: gr32, preferred-register: '', flags: [ ] }
12+
# CHECK: - { id: 3, class: gr16, preferred-register: '', flags: [ ] }
13+
# CHECK: - { id: 4, class: _, preferred-register: '', flags: [ ] }
1414
name: func
1515
body: |
1616
bb.0:

‎llvm/test/CodeGen/MIR/X86/roundtrip.mir‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -2,8 +2,8 @@
22
---
33
# CHECK-LABEL: name: func0
44
# CHECK: registers:
5-
# CHECK: - { id: 0, class: gr32, preferred-register: '' }
6-
# CHECK: - { id: 1, class: gr32, preferred-register: '' }
5+
# CHECK: - { id: 0, class: gr32, preferred-register: '', flags: [ ] }
6+
# CHECK: - { id: 1, class: gr32, preferred-register: '', flags: [ ] }
77
# CHECK: body: |
88
# CHECK: bb.0:
99
# CHECK: %0:gr32 = MOV32r0 implicit-def $eflags

‎llvm/test/CodeGen/MIR/X86/simple-register-allocation-hints.mir‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -15,9 +15,9 @@
1515
name: test
1616
tracksRegLiveness: true
1717
# CHECK: registers:
18-
# CHECK-NEXT: - { id: 0, class: gr32, preferred-register: '' }
19-
# CHECK-NEXT: - { id: 1, class: gr32, preferred-register: '$esi' }
20-
# CHECK-NEXT: - { id: 2, class: gr32, preferred-register: '$edi' }
18+
# CHECK-NEXT: - { id: 0, class: gr32, preferred-register: '', flags: [ ] }
19+
# CHECK-NEXT: - { id: 1, class: gr32, preferred-register: '$esi', flags: [ ] }
20+
# CHECK-NEXT: - { id: 2, class: gr32, preferred-register: '$edi', flags: [ ] }
2121
registers:
2222
- { id: 0, class: gr32 }
2323
- { id: 1, class: gr32, preferred-register: '$esi' }

‎llvm/test/CodeGen/MIR/X86/virtual-registers.mir‎

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -33,9 +33,9 @@
3333
name: bar
3434
tracksRegLiveness: true
3535
# CHECK: registers:
36-
# CHECK-NEXT: - { id: 0, class: gr32, preferred-register: '' }
37-
# CHECK-NEXT: - { id: 1, class: gr32, preferred-register: '' }
38-
# CHECK-NEXT: - { id: 2, class: gr32, preferred-register: '' }
36+
# CHECK-NEXT: - { id: 0, class: gr32, preferred-register: '', flags: [ ] }
37+
# CHECK-NEXT: - { id: 1, class: gr32, preferred-register: '', flags: [ ] }
38+
# CHECK-NEXT: - { id: 2, class: gr32, preferred-register: '', flags: [ ] }
3939
registers:
4040
- { id: 0, class: gr32 }
4141
- { id: 1, class: gr32 }
@@ -67,9 +67,9 @@ name: foo
6767
tracksRegLiveness: true
6868
# CHECK: name: foo
6969
# CHECK: registers:
70-
# CHECK-NEXT: - { id: 0, class: gr32, preferred-register: '' }
71-
# CHECK-NEXT: - { id: 1, class: gr32, preferred-register: '' }
72-
# CHECK-NEXT: - { id: 2, class: gr32, preferred-register: '' }
70+
# CHECK-NEXT: - { id: 0, class: gr32, preferred-register: '', flags: [ ] }
71+
# CHECK-NEXT: - { id: 1, class: gr32, preferred-register: '', flags: [ ] }
72+
# CHECK-NEXT: - { id: 2, class: gr32, preferred-register: '', flags: [ ] }
7373
registers:
7474
- { id: 2, class: gr32 }
7575
- { id: 0, class: gr32 }

‎llvm/test/CodeGen/X86/GlobalISel/legalize-mul-v128.mir‎

Lines changed: 9 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -26,9 +26,9 @@ alignment: 16
2626
legalized: false
2727
regBankSelected: false
2828
# ALL: registers:
29-
# ALL-NEXT: - { id: 0, class: _, preferred-register: '' }
30-
# ALL-NEXT: - { id: 1, class: _, preferred-register: '' }
31-
# ALL-NEXT: - { id: 2, class: _, preferred-register: '' }
29+
# ALL-NEXT: - { id: 0, class: _, preferred-register: '', flags: [ ] }
30+
# ALL-NEXT: - { id: 1, class: _, preferred-register: '', flags: [ ] }
31+
# ALL-NEXT: - { id: 2, class: _, preferred-register: '', flags: [ ] }
3232
registers:
3333
- { id: 0, class: _ }
3434
- { id: 1, class: _ }
@@ -56,9 +56,9 @@ alignment: 16
5656
legalized: false
5757
regBankSelected: false
5858
# ALL: registers:
59-
# ALL-NEXT: - { id: 0, class: _, preferred-register: '' }
60-
# ALL-NEXT: - { id: 1, class: _, preferred-register: '' }
61-
# ALL-NEXT: - { id: 2, class: _, preferred-register: '' }
59+
# ALL-NEXT: - { id: 0, class: _, preferred-register: '', flags: [ ] }
60+
# ALL-NEXT: - { id: 1, class: _, preferred-register: '', flags: [ ] }
61+
# ALL-NEXT: - { id: 2, class: _, preferred-register: '', flags: [ ] }
6262
registers:
6363
- { id: 0, class: _ }
6464
- { id: 1, class: _ }
@@ -86,9 +86,9 @@ alignment: 16
8686
legalized: false
8787
regBankSelected: false
8888
# ALL: registers:
89-
# ALL-NEXT: - { id: 0, class: _, preferred-register: '' }
90-
# ALL-NEXT: - { id: 1, class: _, preferred-register: '' }
91-
# ALL-NEXT: - { id: 2, class: _, preferred-register: '' }
89+
# ALL-NEXT: - { id: 0, class: _, preferred-register: '', flags: [ ] }
90+
# ALL-NEXT: - { id: 1, class: _, preferred-register: '', flags: [ ] }
91+
# ALL-NEXT: - { id: 2, class: _, preferred-register: '', flags: [ ] }
9292
registers:
9393
- { id: 0, class: _ }
9494
- { id: 1, class: _ }

‎llvm/test/CodeGen/X86/GlobalISel/legalize-mul-v256.mir‎

Lines changed: 9 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -26,9 +26,9 @@ alignment: 16
2626
legalized: false
2727
regBankSelected: false
2828
# ALL: registers:
29-
# ALL-NEXT: - { id: 0, class: _, preferred-register: '' }
30-
# ALL-NEXT: - { id: 1, class: _, preferred-register: '' }
31-
# ALL-NEXT: - { id: 2, class: _, preferred-register: '' }
29+
# ALL-NEXT: - { id: 0, class: _, preferred-register: '', flags: [ ] }
30+
# ALL-NEXT: - { id: 1, class: _, preferred-register: '', flags: [ ] }
31+
# ALL-NEXT: - { id: 2, class: _, preferred-register: '', flags: [ ] }
3232
registers:
3333
- { id: 0, class: _ }
3434
- { id: 1, class: _ }
@@ -56,9 +56,9 @@ alignment: 16
5656
legalized: false
5757
regBankSelected: false
5858
# ALL: registers:
59-
# ALL-NEXT: - { id: 0, class: _, preferred-register: '' }
60-
# ALL-NEXT: - { id: 1, class: _, preferred-register: '' }
61-
# ALL-NEXT: - { id: 2, class: _, preferred-register: '' }
59+
# ALL-NEXT: - { id: 0, class: _, preferred-register: '', flags: [ ] }
60+
# ALL-NEXT: - { id: 1, class: _, preferred-register: '', flags: [ ] }
61+
# ALL-NEXT: - { id: 2, class: _, preferred-register: '', flags: [ ] }
6262
registers:
6363
- { id: 0, class: _ }
6464
- { id: 1, class: _ }
@@ -86,9 +86,9 @@ alignment: 16
8686
legalized: false
8787
regBankSelected: false
8888
# ALL: registers:
89-
# ALL-NEXT: - { id: 0, class: _, preferred-register: '' }
90-
# ALL-NEXT: - { id: 1, class: _, preferred-register: '' }
91-
# ALL-NEXT: - { id: 2, class: _, preferred-register: '' }
89+
# ALL-NEXT: - { id: 0, class: _, preferred-register: '', flags: [ ] }
90+
# ALL-NEXT: - { id: 1, class: _, preferred-register: '', flags: [ ] }
91+
# ALL-NEXT: - { id: 2, class: _, preferred-register: '', flags: [ ] }
9292
registers:
9393
- { id: 0, class: _ }
9494
- { id: 1, class: _ }

‎llvm/test/CodeGen/X86/GlobalISel/legalize-mul-v512.mir‎

Lines changed: 9 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -28,9 +28,9 @@ alignment: 16
2828
legalized: false
2929
regBankSelected: false
3030
# ALL: registers:
31-
# ALL-NEXT: - { id: 0, class: _, preferred-register: '' }
32-
# ALL-NEXT: - { id: 1, class: _, preferred-register: '' }
33-
# ALL-NEXT: - { id: 2, class: _, preferred-register: '' }
31+
# ALL-NEXT: - { id: 0, class: _, preferred-register: '', flags: [ ] }
32+
# ALL-NEXT: - { id: 1, class: _, preferred-register: '', flags: [ ] }
33+
# ALL-NEXT: - { id: 2, class: _, preferred-register: '', flags: [ ] }
3434
registers:
3535
- { id: 0, class: _ }
3636
- { id: 1, class: _ }
@@ -58,9 +58,9 @@ alignment: 16
5858
legalized: false
5959
regBankSelected: false
6060
# ALL: registers:
61-
# ALL-NEXT: - { id: 0, class: _, preferred-register: '' }
62-
# ALL-NEXT: - { id: 1, class: _, preferred-register: '' }
63-
# ALL-NEXT: - { id: 2, class: _, preferred-register: '' }
61+
# ALL-NEXT: - { id: 0, class: _, preferred-register: '', flags: [ ] }
62+
# ALL-NEXT: - { id: 1, class: _, preferred-register: '', flags: [ ] }
63+
# ALL-NEXT: - { id: 2, class: _, preferred-register: '', flags: [ ] }
6464
registers:
6565
- { id: 0, class: _ }
6666
- { id: 1, class: _ }
@@ -88,9 +88,9 @@ alignment: 16
8888
legalized: false
8989
regBankSelected: false
9090
# ALL: registers:
91-
# ALL-NEXT: - { id: 0, class: _, preferred-register: '' }
92-
# ALL-NEXT: - { id: 1, class: _, preferred-register: '' }
93-
# ALL-NEXT: - { id: 2, class: _, preferred-register: '' }
91+
# ALL-NEXT: - { id: 0, class: _, preferred-register: '', flags: [ ] }
92+
# ALL-NEXT: - { id: 1, class: _, preferred-register: '', flags: [ ] }
93+
# ALL-NEXT: - { id: 2, class: _, preferred-register: '', flags: [ ] }
9494
registers:
9595
- { id: 0, class: _ }
9696
- { id: 1, class: _ }

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