more

Author: AZero13

llvm/test/DebugInfo/MIR/InstrRef/x86-cmov-converter.mir

@@ -1,3 +1,4 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
 # RUN: llc %s -o - --run-pass=x86-cmov-conversion -mtriple=x86_64-- | FileCheck %s
 # REQUIRES: x86-registered-target
 #
@@ -6,14 +7,6 @@
 # locations. Check that this still works when unfolding memory operands, which
 # involves more decomposition of instructions.
 #
-# CHECK-LABEL: name: CmovInHotPath
-# CHECK-LABEL: bb.3.for.body:
-# CHECK: CMOV32rr {{.*}}, debug-instr-number 1
-#
-# CHECK-LABEL: name: test_cmov_memoperand_in_group_reuse_for_addr2
-# CHECK-LABEL: bb.2.entry:
-# CHECK-NEXT:  PHI {{.*}} debug-instr-number 1,
-# CHECK-NEXT:  PHI {{.*}} debug-instr-number 2,
 --- |
   ; ModuleID = 'x86-cmov-converter.ll'
   source_filename = "x86-cmov-converter.ll"
@@ -110,6 +103,55 @@ liveins:
   - { reg: '$rcx', virtual-reg: '%8' }
 machineFunctionInfo: {}
 body:             |
+  ; CHECK-LABEL: name: CmovInHotPath
+  ; CHECK: bb.0.entry:
+  ; CHECK-NEXT:   successors: %bb.1(0x50000000), %bb.2(0x30000000)
+  ; CHECK-NEXT:   liveins: $edi, $esi, $edx, $rcx
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:gr64 = COPY $rcx
+  ; CHECK-NEXT:   [[COPY1:%[0-9]+]]:gr32 = COPY $edx
+  ; CHECK-NEXT:   [[COPY2:%[0-9]+]]:gr32 = COPY $esi
+  ; CHECK-NEXT:   [[COPY3:%[0-9]+]]:gr32 = COPY $edi
+  ; CHECK-NEXT:   TEST32rr [[COPY3]], [[COPY3]], implicit-def $eflags,  debug-location !12
+  ; CHECK-NEXT:   JCC_1 %bb.2, 14, implicit $eflags
+  ; CHECK-NEXT:   JMP_1 %bb.1
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT: bb.1.for.body.preheader:
+  ; CHECK-NEXT:   successors: %bb.3(0x80000000)
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT:   [[MOV32rr:%[0-9]+]]:gr32 = MOV32rr [[COPY3]],  debug-location !13
+  ; CHECK-NEXT:   [[SUBREG_TO_REG:%[0-9]+]]:gr64 = SUBREG_TO_REG 0, killed [[MOV32rr]], %subreg.sub_32bit,  debug-location !13
+  ; CHECK-NEXT:   JMP_1 %bb.3
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT: bb.2.for.cond.cleanup:
+  ; CHECK-NEXT:   RET 0
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT: bb.3.for.body:
+  ; CHECK-NEXT:   successors: %bb.4(0x40000000), %bb.5(0x40000000)
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT:   [[PHI:%[0-9]+]]:gr64 = PHI [[COPY]], %bb.1, %4, %bb.5
+  ; CHECK-NEXT:   [[PHI1:%[0-9]+]]:gr64 = PHI [[SUBREG_TO_REG]], %bb.1, %3, %bb.5
+  ; CHECK-NEXT:   [[MOV32rm:%[0-9]+]]:gr32 = MOV32rm [[PHI]], 1, $noreg, 0, $noreg,  debug-location !13 :: (load (s32) from %ir.lsr.iv1)
+  ; CHECK-NEXT:   [[INC32r:%[0-9]+]]:gr32 = nsw INC32r [[MOV32rm]], implicit-def dead $eflags,  debug-location !13
+  ; CHECK-NEXT:   [[IMUL32rr:%[0-9]+]]:gr32 = nsw IMUL32rr [[MOV32rm]], [[COPY2]], implicit-def dead $eflags,  debug-location !13
+  ; CHECK-NEXT:   [[SUB32rr:%[0-9]+]]:gr32 = SUB32rr [[IMUL32rr]], [[COPY1]], implicit-def $eflags,  debug-location !13
+  ; CHECK-NEXT:   [[MOV32ri:%[0-9]+]]:gr32 = MOV32ri 10
+  ; CHECK-NEXT:   JCC_1 %bb.5, 15, implicit $eflags,  debug-location !13
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT: bb.4.for.body:
+  ; CHECK-NEXT:   successors: %bb.5(0x80000000)
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT: bb.5.for.body:
+  ; CHECK-NEXT:   successors: %bb.2(0x04000000), %bb.3(0x7c000000)
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT:   [[PHI2:%[0-9]+]]:gr32 = PHI [[INC32r]], %bb.4, [[MOV32ri]], %bb.3,  debug-instr-number 1,  debug-location !13
+  ; CHECK-NEXT:   DBG_INSTR_REF !14, !DIExpression(DW_OP_LLVM_arg, 0), dbg-instr-ref(1, 0),  debug-location !13
+  ; CHECK-NEXT:   [[IMUL32rr1:%[0-9]+]]:gr32 = nsw IMUL32rr [[PHI2]], [[INC32r]], implicit-def dead $eflags,  debug-location !13
+  ; CHECK-NEXT:   MOV32mr [[PHI]], 1, $noreg, 0, $noreg, killed [[IMUL32rr1]],  debug-location !13 :: (store (s32) into %ir.lsr.iv1)
+  ; CHECK-NEXT:   [[ADD64ri8_:%[0-9]+]]:gr64 = ADD64ri8 [[PHI]], 4, implicit-def dead $eflags,  debug-location !13
+  ; CHECK-NEXT:   [[DEC64r:%[0-9]+]]:gr64 = DEC64r [[PHI1]], implicit-def $eflags,  debug-location !13
+  ; CHECK-NEXT:   JCC_1 %bb.2, 4, implicit $eflags,  debug-location !13
+  ; CHECK-NEXT:   JMP_1 %bb.3,  debug-location !13
   bb.0.entry:
     successors: %bb.1(0x50000000), %bb.2(0x30000000)
     liveins: $edi, $esi, $edx, $rcx
@@ -177,6 +219,30 @@ body:             |
   bb.0.entry:
     liveins: $edi, $esi, $rdx, $rcx
 
+    ; CHECK-LABEL: name: test_cmov_memoperand_in_group_reuse_for_addr2
+    ; CHECK: successors: %bb.1(0x40000000), %bb.2(0x40000000)
+    ; CHECK-NEXT: liveins: $edi, $esi, $rdx, $rcx
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY $rcx
+    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:gr64 = COPY $rdx
+    ; CHECK-NEXT: [[COPY2:%[0-9]+]]:gr32 = COPY $esi
+    ; CHECK-NEXT: [[COPY3:%[0-9]+]]:gr32 = COPY $edi
+    ; CHECK-NEXT: [[SUB32rr:%[0-9]+]]:gr32 = SUB32rr [[COPY3]], [[COPY2]], implicit-def $eflags,  debug-location !16
+    ; CHECK-NEXT: JCC_1 %bb.2, 7, implicit $eflags,  debug-location !16
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: .1.entry:
+    ; CHECK-NEXT: successors: %bb.2(0x80000000)
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[MOV64rm:%[0-9]+]]:gr64 = MOV64rm [[COPY]], 1, $noreg, 0, $noreg :: (load (s64) from %ir.y)
+    ; CHECK-NEXT: [[MOV32rm:%[0-9]+]]:gr32 = MOV32rm [[MOV64rm]], 1, $noreg, 0, $noreg :: (load (s32) from %ir.p)
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: .2.entry:
+    ; CHECK-NEXT: [[PHI:%[0-9]+]]:gr64 = PHI [[MOV64rm]], %bb.1, [[COPY1]], %bb.0,  debug-instr-number 1,  debug-location !16
+    ; CHECK-NEXT: [[PHI1:%[0-9]+]]:gr32 = PHI [[MOV32rm]], %bb.1, [[COPY3]], %bb.0,  debug-instr-number 2,  debug-location !16
+    ; CHECK-NEXT: DBG_INSTR_REF !17, !DIExpression(DW_OP_LLVM_arg, 0), dbg-instr-ref(1, 0),  debug-location !16
+    ; CHECK-NEXT: DBG_INSTR_REF !18, !DIExpression(DW_OP_LLVM_arg, 0), dbg-instr-ref(2, 0),  debug-location !16
+    ; CHECK-NEXT: $eax = COPY [[PHI1]],  debug-location !16
+    ; CHECK-NEXT: RET 0, $eax,  debug-location !16
     %3:gr64 = COPY $rcx
     %2:gr64 = COPY $rdx
     %1:gr32 = COPY $esi