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davemgreendavemgreen
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[AArch64][GlobalISel] Add basic GISel test coverage for lround and llround. NFC
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4 files changed

+88
-50
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‎llvm/test/CodeGen/AArch64/llround-conv-fp16.ll‎

Lines changed: 6 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,12 @@
11
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
22
; RUN: llc < %s -mtriple=aarch64 | FileCheck %s --check-prefixes=CHECK-NOFP16
33
; RUN: llc < %s -mtriple=aarch64 -mattr=+fullfp16 | FileCheck %s --check-prefixes=CHECK-FP16
4+
; RUN: llc < %s -mtriple=aarch64 -global-isel -global-isel-abort=2 2>&1 | FileCheck %s --check-prefixes=CHECK-NOFP16,CHECK-GI
5+
; RUN: llc < %s -mtriple=aarch64 -mattr=+fullfp16 -global-isel -global-isel-abort=2 2>&1 | FileCheck %s --check-prefixes=CHECK-FP16,CHECK-GI
6+
7+
; CHECK-GI: warning: Instruction selection used fallback path for testmhhs
8+
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for testmhws
9+
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for testmhxs
410

511
define i16 @testmhhs(half %x) {
612
; CHECK-NOFP16-LABEL: testmhhs:
@@ -55,5 +61,3 @@ entry:
5561
%0 = tail call i64 @llvm.llround.i64.f16(half %x)
5662
ret i64 %0
5763
}
58-
59-
declare i64 @llvm.llround.i64.f16(half) nounwind readnone

‎llvm/test/CodeGen/AArch64/llround-conv.ll‎

Lines changed: 41 additions & 26 deletions
Original file line numberDiff line numberDiff line change
@@ -1,60 +1,75 @@
1+
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
12
; RUN: llc < %s -mtriple=aarch64 -mattr=+neon | FileCheck %s
3+
; RUN: llc < %s -mtriple=aarch64 -mattr=+neon -global-isel -global-isel-abort=2 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-GI
4+
5+
; CHECK-GI: warning: Instruction selection used fallback path for testmswl
6+
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for testmsll
27

3-
; CHECK-LABEL: testmsws:
4-
; CHECK: fcvtas x0, s0
5-
; CHECK: ret
68
define i32 @testmsws(float %x) {
9+
; CHECK-LABEL: testmsws:
10+
; CHECK: // %bb.0: // %entry
11+
; CHECK-NEXT: fcvtas x0, s0
12+
; CHECK-NEXT: // kill: def $w0 killed $w0 killed $x0
13+
; CHECK-NEXT: ret
714
entry:
8-
%0 = tail call i64 @llvm.llround.f32(float %x)
15+
%0 = tail call i64 @llvm.llround.i64.f32(float %x)
916
%conv = trunc i64 %0 to i32
1017
ret i32 %conv
1118
}
1219

13-
; CHECK-LABEL: testmsxs:
14-
; CHECK: fcvtas x0, s0
15-
; CHECK-NEXT: ret
1620
define i64 @testmsxs(float %x) {
21+
; CHECK-LABEL: testmsxs:
22+
; CHECK: // %bb.0: // %entry
23+
; CHECK-NEXT: fcvtas x0, s0
24+
; CHECK-NEXT: ret
1725
entry:
18-
%0 = tail call i64 @llvm.llround.f32(float %x)
26+
%0 = tail call i64 @llvm.llround.i64.f32(float %x)
1927
ret i64 %0
2028
}
2129

22-
; CHECK-LABEL: testmswd:
23-
; CHECK: fcvtas x0, d0
24-
; CHECK: ret
2530
define i32 @testmswd(double %x) {
31+
; CHECK-LABEL: testmswd:
32+
; CHECK: // %bb.0: // %entry
33+
; CHECK-NEXT: fcvtas x0, d0
34+
; CHECK-NEXT: // kill: def $w0 killed $w0 killed $x0
35+
; CHECK-NEXT: ret
2636
entry:
27-
%0 = tail call i64 @llvm.llround.f64(double %x)
37+
%0 = tail call i64 @llvm.llround.i64.f64(double %x)
2838
%conv = trunc i64 %0 to i32
2939
ret i32 %conv
3040
}
3141

32-
; CHECK-LABEL: testmsxd:
33-
; CHECK: fcvtas x0, d0
34-
; CHECK-NEXT: ret
3542
define i64 @testmsxd(double %x) {
43+
; CHECK-LABEL: testmsxd:
44+
; CHECK: // %bb.0: // %entry
45+
; CHECK-NEXT: fcvtas x0, d0
46+
; CHECK-NEXT: ret
3647
entry:
37-
%0 = tail call i64 @llvm.llround.f64(double %x)
48+
%0 = tail call i64 @llvm.llround.i64.f64(double %x)
3849
ret i64 %0
3950
}
4051

41-
; CHECK-LABEL: testmswl:
42-
; CHECK: bl llroundl
4352
define i32 @testmswl(fp128 %x) {
53+
; CHECK-LABEL: testmswl:
54+
; CHECK: // %bb.0: // %entry
55+
; CHECK-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill
56+
; CHECK-NEXT: .cfi_def_cfa_offset 16
57+
; CHECK-NEXT: .cfi_offset w30, -16
58+
; CHECK-NEXT: bl llroundl
59+
; CHECK-NEXT: // kill: def $w0 killed $w0 killed $x0
60+
; CHECK-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload
61+
; CHECK-NEXT: ret
4462
entry:
45-
%0 = tail call i64 @llvm.llround.f128(fp128 %x)
63+
%0 = tail call i64 @llvm.llround.i64.f128(fp128 %x)
4664
%conv = trunc i64 %0 to i32
4765
ret i32 %conv
4866
}
4967

50-
; CHECK-LABEL: testmsll:
51-
; CHECK: b llroundl
5268
define i64 @testmsll(fp128 %x) {
69+
; CHECK-LABEL: testmsll:
70+
; CHECK: // %bb.0: // %entry
71+
; CHECK-NEXT: b llroundl
5372
entry:
54-
%0 = tail call i64 @llvm.llround.f128(fp128 %x)
73+
%0 = tail call i64 @llvm.llround.i64.f128(fp128 %x)
5574
ret i64 %0
5675
}
57-
58-
declare i64 @llvm.llround.f32(float) nounwind readnone
59-
declare i64 @llvm.llround.f64(double) nounwind readnone
60-
declare i64 @llvm.llround.f128(fp128) nounwind readnone

‎llvm/test/CodeGen/AArch64/lround-conv-fp16.ll‎

Lines changed: 6 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,12 @@
11
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
22
; RUN: llc < %s -mtriple=aarch64 | FileCheck %s --check-prefixes=CHECK-NOFP16
33
; RUN: llc < %s -mtriple=aarch64 -mattr=+fullfp16 | FileCheck %s --check-prefixes=CHECK-FP16
4+
; RUN: llc < %s -mtriple=aarch64 -global-isel -global-isel-abort=2 2>&1 | FileCheck %s --check-prefixes=CHECK-NOFP16,CHECK-GI
5+
; RUN: llc < %s -mtriple=aarch64 -mattr=+fullfp16 -global-isel -global-isel-abort=2 2>&1 | FileCheck %s --check-prefixes=CHECK-FP16,CHECK-GI
6+
7+
; CHECK-GI: warning: Instruction selection used fallback path for testmhhs
8+
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for testmhws
9+
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for testmhxs
410

511
define i16 @testmhhs(half %x) {
612
; CHECK-NOFP16-LABEL: testmhhs:
@@ -55,5 +61,3 @@ entry:
5561
%0 = tail call i64 @llvm.lround.i64.f16(half %x)
5662
ret i64 %0
5763
}
58-
59-
declare i64 @llvm.lround.i64.f16(half) nounwind readnone

‎llvm/test/CodeGen/AArch64/lround-conv.ll‎

Lines changed: 35 additions & 20 deletions
Original file line numberDiff line numberDiff line change
@@ -1,60 +1,75 @@
1+
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
12
; RUN: llc < %s -mtriple=aarch64 -mattr=+neon | FileCheck %s
3+
; RUN: llc < %s -mtriple=aarch64 -mattr=+neon -global-isel -global-isel-abort=2 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-GI
4+
5+
; CHECK-GI: warning: Instruction selection used fallback path for testmswl
6+
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for testmsll
27

3-
; CHECK-LABEL: testmsws:
4-
; CHECK: fcvtas x0, s0
5-
; CHECK: ret
68
define i32 @testmsws(float %x) {
9+
; CHECK-LABEL: testmsws:
10+
; CHECK: // %bb.0: // %entry
11+
; CHECK-NEXT: fcvtas x0, s0
12+
; CHECK-NEXT: // kill: def $w0 killed $w0 killed $x0
13+
; CHECK-NEXT: ret
714
entry:
815
%0 = tail call i64 @llvm.lround.i64.f32(float %x)
916
%conv = trunc i64 %0 to i32
1017
ret i32 %conv
1118
}
1219

13-
; CHECK-LABEL: testmsxs:
14-
; CHECK: fcvtas x0, s0
15-
; CHECK-NEXT: ret
1620
define i64 @testmsxs(float %x) {
21+
; CHECK-LABEL: testmsxs:
22+
; CHECK: // %bb.0: // %entry
23+
; CHECK-NEXT: fcvtas x0, s0
24+
; CHECK-NEXT: ret
1725
entry:
1826
%0 = tail call i64 @llvm.lround.i64.f32(float %x)
1927
ret i64 %0
2028
}
2129

22-
; CHECK-LABEL: testmswd:
23-
; CHECK: fcvtas x0, d0
24-
; CHECK: ret
2530
define i32 @testmswd(double %x) {
31+
; CHECK-LABEL: testmswd:
32+
; CHECK: // %bb.0: // %entry
33+
; CHECK-NEXT: fcvtas x0, d0
34+
; CHECK-NEXT: // kill: def $w0 killed $w0 killed $x0
35+
; CHECK-NEXT: ret
2636
entry:
2737
%0 = tail call i64 @llvm.lround.i64.f64(double %x)
2838
%conv = trunc i64 %0 to i32
2939
ret i32 %conv
3040
}
3141

32-
; CHECK-LABEL: testmsxd:
33-
; CHECK: fcvtas x0, d0
34-
; CHECK-NEXT: ret
3542
define i64 @testmsxd(double %x) {
43+
; CHECK-LABEL: testmsxd:
44+
; CHECK: // %bb.0: // %entry
45+
; CHECK-NEXT: fcvtas x0, d0
46+
; CHECK-NEXT: ret
3647
entry:
3748
%0 = tail call i64 @llvm.lround.i64.f64(double %x)
3849
ret i64 %0
3950
}
4051

41-
; CHECK-LABEL: testmswl:
42-
; CHECK: bl lroundl
4352
define i32 @testmswl(fp128 %x) {
53+
; CHECK-LABEL: testmswl:
54+
; CHECK: // %bb.0: // %entry
55+
; CHECK-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill
56+
; CHECK-NEXT: .cfi_def_cfa_offset 16
57+
; CHECK-NEXT: .cfi_offset w30, -16
58+
; CHECK-NEXT: bl lroundl
59+
; CHECK-NEXT: // kill: def $w0 killed $w0 killed $x0
60+
; CHECK-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload
61+
; CHECK-NEXT: ret
4462
entry:
4563
%0 = tail call i64 @llvm.lround.i64.f128(fp128 %x)
4664
%conv = trunc i64 %0 to i32
4765
ret i32 %conv
4866
}
4967

50-
; CHECK-LABEL: testmsll:
51-
; CHECK: b lroundl
5268
define i64 @testmsll(fp128 %x) {
69+
; CHECK-LABEL: testmsll:
70+
; CHECK: // %bb.0: // %entry
71+
; CHECK-NEXT: b lroundl
5372
entry:
5473
%0 = tail call i64 @llvm.lround.i64.f128(fp128 %x)
5574
ret i64 %0
5675
}
57-
58-
declare i64 @llvm.lround.i64.f32(float) nounwind readnone
59-
declare i64 @llvm.lround.i64.f64(double) nounwind readnone
60-
declare i64 @llvm.lround.i64.f128(fp128) nounwind readnone

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