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Revise zicond with zfinx implement
* CondV should always be int, no need to check * Omit the if statement bracket when there is only oneline body
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llvm/lib/Target/RISCV/RISCVISelLowering.cpp

Lines changed: 10 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -9559,18 +9559,18 @@ SDValue RISCVTargetLowering::lowerSELECT(SDValue Op, SelectionDAG &DAG) const {
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// floating value when CondV is int type
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bool FPinGPR = Subtarget.hasStdExtZfinx();
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bool UseZicondForFPSel = Subtarget.hasStdExtZicond() && FPinGPR &&
9562-
VT.isFloatingPoint() &&
9563-
CondV.getValueType().isInteger();
9562+
VT.isFloatingPoint();
9563+
95649564
if (UseZicondForFPSel) {
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MVT XLenIntVT = Subtarget.getXLenVT();
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auto CastToInt = [&](SDValue V) -> SDValue {
9568-
if (VT == MVT::f16) {
9568+
if (VT == MVT::f16)
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return DAG.getNode(RISCVISD::FMV_X_ANYEXTH, DL, XLenIntVT, V);
9570-
}
9571-
if (VT == MVT::f32 && Subtarget.is64Bit()) {
9570+
9571+
if (VT == MVT::f32 && Subtarget.is64Bit())
95729572
return DAG.getNode(RISCVISD::FMV_X_ANYEXTW_RV64, DL, XLenIntVT, V);
9573-
}
9573+
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return DAG.getBitcast(XLenIntVT, V);
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};
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@@ -9582,12 +9582,12 @@ SDValue RISCVTargetLowering::lowerSELECT(SDValue Op, SelectionDAG &DAG) const {
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DAG.getNode(ISD::SELECT, DL, XLenIntVT, CondV, TrueVInt, FalseVInt);
95839583

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// Convert back to floating VT
9585-
if (VT == MVT::f32 && Subtarget.is64Bit()) {
9585+
if (VT == MVT::f32 && Subtarget.is64Bit())
95869586
return DAG.getNode(RISCVISD::FMV_W_X_RV64, DL, VT, ResultInt);
9587-
}
9588-
if (VT == MVT::f16) {
9587+
9588+
if (VT == MVT::f16)
95899589
return DAG.getNode(RISCVISD::FMV_H_X, DL, VT, ResultInt);
9590-
}
9590+
95919591
return DAG.getBitcast(VT, ResultInt);
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}
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