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[PowerPC] Add Dense Math binary integer outer-Product accumulate to DMR Instructions (#130791)
This commit adds the following Dense Math Facility integer calculation instructions: dmxvi8gerx4, dmxvi8gerx4pp, dmxvi8gerx4spp, pmdmxvi8gerx4, pmdmxvi8gerx4pp, and pmdmxvi8gerx4spp, along with their corresponding intrinsics and tests.
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‎llvm/include/llvm/IR/IntrinsicsPowerPC.td‎

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@@ -280,6 +280,13 @@ multiclass PowerPC_MMA_ACC_PP_Intrinsic<list<LLVMType> args> {
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[IntrNoMem]>;
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}
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multiclass PowerPC_MMA_DMR_PP_Intrinsic<list<LLVMType> args> {
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def NAME: DefaultAttrsIntrinsic<[llvm_v1024i1_ty], args, [IntrNoMem]>;
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def pp : DefaultAttrsIntrinsic<[llvm_v1024i1_ty],
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!listconcat([llvm_v1024i1_ty], args),
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[IntrNoMem]>;
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}
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//===----------------------------------------------------------------------===//
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// PowerPC Altivec Intrinsic Class Definitions.
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//
@@ -1711,6 +1718,20 @@ let TargetPrefix = "ppc" in {
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[llvm_v512i1_ty, llvm_v16i8_ty, llvm_v16i8_ty,
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llvm_i32_ty, llvm_i32_ty, llvm_i32_ty],
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[IntrNoMem]>;
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defm int_ppc_mma_dmxvi8gerx4 :
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PowerPC_MMA_DMR_PP_Intrinsic<[llvm_v256i1_ty, llvm_v16i8_ty]>;
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defm int_ppc_mma_pmdmxvi8gerx4 :
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PowerPC_MMA_DMR_PP_Intrinsic<[llvm_v256i1_ty, llvm_v16i8_ty, llvm_i32_ty,
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llvm_i32_ty, llvm_i32_ty]>;
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def int_ppc_mma_dmxvi8gerx4spp :
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DefaultAttrsIntrinsic<[llvm_v1024i1_ty],
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[llvm_v1024i1_ty, llvm_v256i1_ty, llvm_v16i8_ty],
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[IntrNoMem]>;
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def int_ppc_mma_pmdmxvi8gerx4spp :
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DefaultAttrsIntrinsic<[llvm_v1024i1_ty],
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[llvm_v1024i1_ty, llvm_v256i1_ty, llvm_v16i8_ty,
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llvm_i32_ty, llvm_i32_ty, llvm_i32_ty],
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[IntrNoMem]>;
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}
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// XL Compat intrinsics.

‎llvm/lib/Target/PowerPC/PPCInstrFutureMMA.td‎

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@@ -69,6 +69,96 @@ class XForm_ATB3<bits<6> opcode, bits<5> o, bits<10> xo, dag OOL, dag IOL,
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let Inst{31} = 0;
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}
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class XX3Form_AT3_XAp5B6<bits<6> opcode, bits<8> xo, dag OOL, dag IOL,
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string asmstr, InstrItinClass itin,
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list<dag> pattern>
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: I<opcode, OOL, IOL, asmstr, itin> {
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bits<3> AT;
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bits<5> XAp;
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bits<6> XB;
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let Pattern = pattern;
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let Inst{6-8} = AT;
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let Inst{9-10} = 0;
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let Inst{11-14} = XAp{3-0};
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let Inst{15} = 0;
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let Inst{16-20} = XB{4-0};
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let Inst{21-28} = xo;
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let Inst{29} = XAp{4};
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let Inst{30} = XB{5};
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let Inst{31} = 0;
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}
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class MMIRR_XX3Form_X8YP4_XAp5B6<bits<6> opcode, bits<8> xo, dag OOL, dag IOL,
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string asmstr, InstrItinClass itin,
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list<dag> pattern>
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: PI<1, opcode, OOL, IOL, asmstr, itin> {
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bits<3> AT;
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bits<6> XAp;
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bits<6> XB;
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bits<8> XMSK;
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bits<4> YMSK;
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bits<4> PMSK;
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let Pattern = pattern;
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// The prefix.
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let Inst{6-7} = 3;
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let Inst{8-11} = 9;
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let Inst{12-15} = 0;
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let Inst{16-19} = PMSK;
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let Inst{20-27} = XMSK;
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let Inst{28-31} = YMSK;
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// The instruction.
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let Inst{38-40} = AT;
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let Inst{41-42} = 0;
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let Inst{43-46} = XAp{3-0};
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let Inst{47} = 0;
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let Inst{48-52} = XB{4-0};
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let Inst{53-60} = xo;
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let Inst{61} = XAp{4};
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let Inst{62} = XB{5};
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let Inst{63} = 0;
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}
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multiclass DMR_UM_XOEO<bits<6> opcode, bits<8> xo, dag IOL, string asmbase,
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string asmstr> {
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let Predicates = [MMA, IsISAFuture] in {
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def NAME :
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XX3Form_AT3_XAp5B6<opcode, !or(xo, 0x01), (outs dmr:$AT), IOL,
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!strconcat(asmbase#" ", asmstr), IIC_VecFP, []>,
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RegConstraint<"@earlyclobber $AT">;
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def PP :
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XX3Form_AT3_XAp5B6<opcode, xo, (outs dmr:$AT), !con((ins dmr:$ATi), IOL),
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!strconcat(asmbase#"pp ", asmstr), IIC_VecFP, []>,
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RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">;
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}
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}
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multiclass DMR_UM_M448_XOEO<bits<6> opcode, bits<8> xo, dag IOL, string asmbase,
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string asmstr> {
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defm NAME : DMR_UM_XOEO<opcode, xo, IOL, asmbase, asmstr>;
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let Predicates = [MMA, PrefixInstrs, IsISAFuture] in {
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def PM#NAME :
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MMIRR_XX3Form_X8YP4_XAp5B6<
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opcode, !or(xo, 0x01), (outs dmr:$AT),
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!con(IOL, (ins u8imm:$XMSK, u4imm:$YMSK, u4imm:$PMSK)),
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!strconcat("pm"#asmbase#" ", asmstr#", $XMSK, $YMSK, $PMSK"),
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IIC_VecFP, []>,
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RegConstraint<"@earlyclobber $AT">;
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def PM#NAME#PP :
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MMIRR_XX3Form_X8YP4_XAp5B6<
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opcode, xo, (outs dmr:$AT),
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!con((ins dmr:$ATi),
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!con(IOL, (ins u8imm:$XMSK, u4imm:$YMSK, u4imm:$PMSK))),
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!strconcat("pm"#asmbase#"pp ", asmstr#", $XMSK, $YMSK, $PMSK"),
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IIC_VecFP, []>,
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RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">;
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}
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}
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let Predicates = [IsISAFuture] in {
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def DMXXEXTFDMR512 : XX3Form_AT3_XABp5_P1<60, 226,
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(outs vsrprc:$XAp, vsrprc:$XBp),
@@ -117,3 +207,56 @@ let Predicates = [IsISAFuture] in {
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"dmsetdmrz $AT", NoItinerary,
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[(set v1024i1:$AT, (int_ppc_mma_dmsetdmrz))]>;
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}
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// MMA+ accumulating/non-accumulating instructions.
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// DMXVI8GERX4, DMXVI8GERX4PP, PMDMXVI8GERX4, PMDMXVI8GERX4PP
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defm DMXVI8GERX4 : DMR_UM_M448_XOEO<59, 10, (ins vsrprc:$XAp, vsrc:$XB),
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"dmxvi8gerx4", "$AT, $XAp, $XB">;
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let Predicates = [MMA, IsISAFuture] in {
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def DMXVI8GERX4SPP :
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XX3Form_AT3_XAp5B6<59, 98, (outs dmr:$AT), (ins dmr:$ATi, vsrprc:$XAp, vsrc:$XB),
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"dmxvi8gerx4spp $AT, $XAp, $XB", IIC_VecGeneral, []>,
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RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">;
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}
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let Predicates = [MMA, PrefixInstrs, IsISAFuture] in {
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def PMDMXVI8GERX4SPP :
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MMIRR_XX3Form_X8YP4_XAp5B6<59, 98, (outs dmr:$AT),
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(ins dmr:$ATi, vsrprc:$XAp,vsrc:$XB, u8imm:$XMSK,
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u4imm:$YMSK, u4imm:$PMSK),
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"pmdmxvi8gerx4spp $AT, $XAp, $XB, $XMSK, $YMSK, $PMSK",
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IIC_VecGeneral, []>,
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RegConstraint<"$ATi = $AT">, NoEncode<"$ATi">;
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}
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// MMA+ Intrinsics
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let Predicates = [MMA, IsISAFuture] in {
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def : Pat<(v1024i1 (int_ppc_mma_dmxvi8gerx4 v256i1:$XAp, v16i8:$XB)),
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(DMXVI8GERX4 $XAp, RCCp.BToVSRC)>;
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def : Pat<(v1024i1 (int_ppc_mma_dmxvi8gerx4pp v1024i1:$ATi, v256i1:$XAp, v16i8:$XB)),
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(DMXVI8GERX4PP $ATi, $XAp, RCCp.BToVSRC)>;
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def : Pat<(v1024i1 (int_ppc_mma_dmxvi8gerx4spp v1024i1:$ATi, v256i1:$XAp, v16i8:$XB)),
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(DMXVI8GERX4SPP $ATi, $XAp, RCCp.BToVSRC)>;
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}
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let Predicates = [MMA, PrefixInstrs, IsISAFuture] in {
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def : Pat<(v1024i1 (int_ppc_mma_pmdmxvi8gerx4 v256i1:$XAp, v16i8:$XB, Msk8Imm:$XMSK,
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Msk4Imm:$YMSK, Msk4Imm:$PMSK)),
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(PMDMXVI8GERX4 $XAp, RCCp.BToVSRC, Msk8Imm:$XMSK,
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Msk4Imm:$YMSK, Msk4Imm:$PMSK)>;
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def : Pat<(v1024i1 (int_ppc_mma_pmdmxvi8gerx4pp v1024i1:$ATi, v256i1:$XAp, v16i8:$XB,
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Msk8Imm:$XMSK, Msk4Imm:$YMSK,
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Msk4Imm:$PMSK)),
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(PMDMXVI8GERX4PP $ATi, $XAp, RCCp.BToVSRC, Msk8Imm:$XMSK,
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Msk4Imm:$YMSK, Msk4Imm:$PMSK)>;
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def : Pat<(v1024i1 (int_ppc_mma_pmdmxvi8gerx4spp v1024i1:$ATi, v256i1:$XAp, v16i8:$XB,
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Msk8Imm:$XMSK, Msk4Imm:$YMSK,
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Msk4Imm:$PMSK)),
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(PMDMXVI8GERX4SPP $ATi, $XAp, RCCp.BToVSRC, Msk8Imm:$XMSK,
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Msk4Imm:$YMSK, Msk4Imm:$PMSK)>;
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}

‎llvm/lib/Target/PowerPC/PPCInstrInfo.td‎

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@@ -3474,6 +3474,13 @@ class PPCAsmPseudo<string asm, dag iops>
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let TSFlags{10} = MemriOp;
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}
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// Mask immediates for MMA instructions (2, 4 and 8 bits).
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def Msk2Imm : ImmLeaf<i32, [{ return isUInt<2>(Imm); }]>;
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def Msk4Imm : ImmLeaf<i32, [{ return isUInt<4>(Imm); }]>;
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def Msk8Imm : ImmLeaf<i32, [{ return isUInt<8>(Imm); }]>;
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def MMA : Predicate<"Subtarget->hasMMA()">;
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// Prefixed instructions may require access to the above defs at a later
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// time so we include this after the def.
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include "PPCInstrP10.td"

‎llvm/lib/Target/PowerPC/PPCInstrMMA.td‎

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@@ -1,12 +1,4 @@
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// Mask immediates for MMA instructions (2, 4 and 8 bits).
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def Msk2Imm : ImmLeaf<i32, [{ return isUInt<2>(Imm); }]>;
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def Msk4Imm : ImmLeaf<i32, [{ return isUInt<4>(Imm); }]>;
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def Msk8Imm : ImmLeaf<i32, [{ return isUInt<8>(Imm); }]>;
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def MMA : Predicate<"Subtarget->hasMMA()">;
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9-
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// Multiclass definitions for MMA accumulator instructions.
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// ----------------------------------------------------------------------------
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