@@ -1086,9 +1086,10 @@ bool DAGCombiner::reassociationCanBreakAddressingModePattern(unsigned Opc,
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// (load/store (add/sub (add x, y), vscale))
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// (load/store (add/sub (add x, y), (lsl vscale, C)))
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// (load/store (add/sub (add x, y), (mul vscale, C)))
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- if (sd_match(N1, m_AnyOf(m_VScale(m_Value()),
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- m_Shl(m_VScale(m_Value()), m_ConstInt()),
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- m_Mul(m_VScale(m_Value()), m_ConstInt()))) &&
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+ if ((N1.getOpcode() == ISD::VSCALE ||
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+ ((N1.getOpcode() == ISD::SHL || N1.getOpcode() == ISD::MUL) &&
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+ N1.getOperand(0).getOpcode() == ISD::VSCALE &&
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+ isa<ConstantSDNode>(N1.getOperand(1)))) &&
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N1.getValueType().getFixedSizeInBits() <= 64) {
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int64_t ScalableOffset = N1.getOpcode() == ISD::VSCALE
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? N1.getConstantOperandVal(0)
@@ -2974,7 +2975,8 @@ SDValue DAGCombiner::visitADD(SDNode *N) {
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}
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// fold a+vscale(c1)+vscale(c2) -> a+vscale(c1+c2)
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- if (sd_match(N0, m_Add(m_Value(), m_VScale(m_Value()))) &&
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+ if (N0.getOpcode() == ISD::ADD &&
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+ N0.getOperand(1).getOpcode() == ISD::VSCALE &&
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N1.getOpcode() == ISD::VSCALE) {
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const APInt &VS0 = N0.getOperand(1)->getConstantOperandAPInt(0);
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const APInt &VS1 = N1->getConstantOperandAPInt(0);
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