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Add tests for bf16/zvfbfmin
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‎llvm/test/CodeGen/RISCV/rvv/vreductions-fp-sdnode-bf16.ll‎

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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv32 -mattr=+d,+zfbfmin,+zvfbfmin,+v -target-abi=ilp32d \
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; RUN: -verify-machineinstrs < %s | FileCheck %s
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; RUN: llc -mtriple=riscv64 -mattr=+d,+zfbfmin,+zvfbfmin,+v -target-abi=lp64d \
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; RUN: -verify-machineinstrs < %s | FileCheck %s
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define bfloat @vreduce_fmin_nxv4f16(<vscale x 4 x bfloat> %val) {
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; CHECK-LABEL: vreduce_fmin_nxv4f16:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma
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; CHECK-NEXT: vfwcvtbf16.f.f.v v10, v8
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; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
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; CHECK-NEXT: vfredmin.vs v8, v10, v10
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; CHECK-NEXT: vfmv.f.s fa5, v8
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; CHECK-NEXT: fcvt.bf16.s fa0, fa5
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; CHECK-NEXT: ret
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%s = call bfloat @llvm.vector.reduce.fmin.nxv4f16(<vscale x 4 x bfloat> %val)
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ret bfloat %s
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}
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define bfloat @vreduce_fmax_nxv4f16(<vscale x 4 x bfloat> %val) {
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; CHECK-LABEL: vreduce_fmax_nxv4f16:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma
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; CHECK-NEXT: vfwcvtbf16.f.f.v v10, v8
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; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
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; CHECK-NEXT: vfredmax.vs v8, v10, v10
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; CHECK-NEXT: vfmv.f.s fa5, v8
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; CHECK-NEXT: fcvt.bf16.s fa0, fa5
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; CHECK-NEXT: ret
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%s = call bfloat @llvm.vector.reduce.fmax.nxv4f16(<vscale x 4 x bfloat> %val)
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ret bfloat %s
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}
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define bfloat @vreduce_fmin_nnan_nxv4f16(<vscale x 4 x bfloat> %val) {
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; CHECK-LABEL: vreduce_fmin_nnan_nxv4f16:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma
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; CHECK-NEXT: vfwcvtbf16.f.f.v v10, v8
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; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
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; CHECK-NEXT: vfredmin.vs v8, v10, v10
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; CHECK-NEXT: vfmv.f.s fa5, v8
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; CHECK-NEXT: fcvt.bf16.s fa0, fa5
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; CHECK-NEXT: ret
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%s = call nnan bfloat @llvm.vector.reduce.fmin.nxv4f16(<vscale x 4 x bfloat> %val)
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ret bfloat %s
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}
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define bfloat @vreduce_fmax_nnan_nxv4f16(<vscale x 4 x bfloat> %val) {
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; CHECK-LABEL: vreduce_fmax_nnan_nxv4f16:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma
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; CHECK-NEXT: vfwcvtbf16.f.f.v v10, v8
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; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
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; CHECK-NEXT: vfredmax.vs v8, v10, v10
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; CHECK-NEXT: vfmv.f.s fa5, v8
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; CHECK-NEXT: fcvt.bf16.s fa0, fa5
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; CHECK-NEXT: ret
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%s = call nnan bfloat @llvm.vector.reduce.fmax.nxv4f16(<vscale x 4 x bfloat> %val)
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ret bfloat %s
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}
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define bfloat @vreduce_fminimum_nxv4f16(<vscale x 4 x bfloat> %val) {
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; CHECK-LABEL: vreduce_fminimum_nxv4f16:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma
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; CHECK-NEXT: vfwcvtbf16.f.f.v v10, v8
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; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
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; CHECK-NEXT: vmfne.vv v8, v10, v10
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; CHECK-NEXT: vcpop.m a0, v8
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; CHECK-NEXT: beqz a0, .LBB4_2
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; CHECK-NEXT: # %bb.1:
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; CHECK-NEXT: lui a0, 523264
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; CHECK-NEXT: fmv.w.x fa5, a0
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; CHECK-NEXT: fcvt.bf16.s fa0, fa5
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; CHECK-NEXT: ret
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; CHECK-NEXT: .LBB4_2:
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; CHECK-NEXT: vfredmin.vs v8, v10, v10
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; CHECK-NEXT: vfmv.f.s fa5, v8
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; CHECK-NEXT: fcvt.bf16.s fa0, fa5
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; CHECK-NEXT: ret
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%s = call bfloat @llvm.vector.reduce.fminimum.nxv4f16(<vscale x 4 x bfloat> %val)
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ret bfloat %s
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}
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define bfloat @vreduce_fmaximum_nxv4f16(<vscale x 4 x bfloat> %val) {
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; CHECK-LABEL: vreduce_fmaximum_nxv4f16:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma
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; CHECK-NEXT: vfwcvtbf16.f.f.v v10, v8
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; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
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; CHECK-NEXT: vmfne.vv v8, v10, v10
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; CHECK-NEXT: vcpop.m a0, v8
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; CHECK-NEXT: beqz a0, .LBB5_2
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; CHECK-NEXT: # %bb.1:
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; CHECK-NEXT: lui a0, 523264
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; CHECK-NEXT: fmv.w.x fa5, a0
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; CHECK-NEXT: fcvt.bf16.s fa0, fa5
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; CHECK-NEXT: ret
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; CHECK-NEXT: .LBB5_2:
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; CHECK-NEXT: vfredmax.vs v8, v10, v10
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; CHECK-NEXT: vfmv.f.s fa5, v8
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; CHECK-NEXT: fcvt.bf16.s fa0, fa5
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; CHECK-NEXT: ret
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%s = call bfloat @llvm.vector.reduce.fmaximum.nxv4f16(<vscale x 4 x bfloat> %val)
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ret bfloat %s
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}
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define bfloat @vreduce_fminimum_nnan_nxv4f16(<vscale x 4 x bfloat> %val) {
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; CHECK-LABEL: vreduce_fminimum_nnan_nxv4f16:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma
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; CHECK-NEXT: vfwcvtbf16.f.f.v v10, v8
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; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
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; CHECK-NEXT: vfredmin.vs v8, v10, v10
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; CHECK-NEXT: vfmv.f.s fa5, v8
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; CHECK-NEXT: fcvt.bf16.s fa0, fa5
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; CHECK-NEXT: ret
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%s = call nnan bfloat @llvm.vector.reduce.fminimum.nxv4f16(<vscale x 4 x bfloat> %val)
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ret bfloat %s
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}
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define bfloat @vreduce_fmaximum_nnan_nxv4f16(<vscale x 4 x bfloat> %val) {
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; CHECK-LABEL: vreduce_fmaximum_nnan_nxv4f16:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma
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; CHECK-NEXT: vfwcvtbf16.f.f.v v10, v8
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; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
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; CHECK-NEXT: vfredmax.vs v8, v10, v10
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; CHECK-NEXT: vfmv.f.s fa5, v8
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; CHECK-NEXT: fcvt.bf16.s fa0, fa5
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; CHECK-NEXT: ret
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%s = call nnan bfloat @llvm.vector.reduce.fmaximum.nxv4f16(<vscale x 4 x bfloat> %val)
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ret bfloat %s
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}
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‎llvm/test/CodeGen/RISCV/rvv/vreductions-fp-vp-bf16.ll‎

Lines changed: 167 additions & 0 deletions
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv32 -mattr=+d,+zfbfmin,+zvfbfmin,+v -target-abi=ilp32d \
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; RUN: -verify-machineinstrs < %s | FileCheck %s
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; RUN: llc -mtriple=riscv64 -mattr=+d,+zfbfmin,+zvfbfmin,+v -target-abi=lp64d \
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; RUN: -verify-machineinstrs < %s | FileCheck %s
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define bfloat @vpreduce_fmin_nxv4f16(bfloat %start, <vscale x 4 x bfloat> %val, <vscale x 4 x i1> %m, i32 zeroext %evl) {
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; CHECK-LABEL: vpreduce_fmin_nxv4f16:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma
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; CHECK-NEXT: vfwcvtbf16.f.f.v v10, v8
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; CHECK-NEXT: fcvt.s.bf16 fa5, fa0
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; CHECK-NEXT: vsetivli zero, 1, e32, m2, ta, ma
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; CHECK-NEXT: vfmv.s.f v8, fa5
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; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma
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; CHECK-NEXT: vfredmin.vs v8, v10, v8, v0.t
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; CHECK-NEXT: vfmv.f.s fa5, v8
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; CHECK-NEXT: fcvt.bf16.s fa0, fa5
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; CHECK-NEXT: ret
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%s = call bfloat @llvm.vp.reduce.fmin.nxv4f16(bfloat %start, <vscale x 4 x bfloat> %val, <vscale x 4 x i1> %m, i32 %evl)
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ret bfloat %s
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}
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define bfloat @vpreduce_fmax_nxv4f16(bfloat %start, <vscale x 4 x bfloat> %val, <vscale x 4 x i1> %m, i32 zeroext %evl) {
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; CHECK-LABEL: vpreduce_fmax_nxv4f16:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma
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; CHECK-NEXT: vfwcvtbf16.f.f.v v10, v8
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; CHECK-NEXT: fcvt.s.bf16 fa5, fa0
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; CHECK-NEXT: vsetivli zero, 1, e32, m2, ta, ma
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; CHECK-NEXT: vfmv.s.f v8, fa5
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; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma
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; CHECK-NEXT: vfredmax.vs v8, v10, v8, v0.t
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; CHECK-NEXT: vfmv.f.s fa5, v8
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; CHECK-NEXT: fcvt.bf16.s fa0, fa5
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; CHECK-NEXT: ret
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%s = call bfloat @llvm.vp.reduce.fmax.nxv4f16(bfloat %start, <vscale x 4 x bfloat> %val, <vscale x 4 x i1> %m, i32 %evl)
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ret bfloat %s
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}
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define bfloat @vpreduce_fmin_nnan_nxv4f16(bfloat %start, <vscale x 4 x bfloat> %val, <vscale x 4 x i1> %m, i32 zeroext %evl) {
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; CHECK-LABEL: vpreduce_fmin_nnan_nxv4f16:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma
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; CHECK-NEXT: vfwcvtbf16.f.f.v v10, v8
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; CHECK-NEXT: fcvt.s.bf16 fa5, fa0
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; CHECK-NEXT: vsetivli zero, 1, e32, m2, ta, ma
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; CHECK-NEXT: vfmv.s.f v8, fa5
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; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma
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; CHECK-NEXT: vfredmin.vs v8, v10, v8, v0.t
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; CHECK-NEXT: vfmv.f.s fa5, v8
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; CHECK-NEXT: fcvt.bf16.s fa0, fa5
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; CHECK-NEXT: ret
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%s = call nnan bfloat @llvm.vp.reduce.fmin.nxv4f16(bfloat %start, <vscale x 4 x bfloat> %val, <vscale x 4 x i1> %m, i32 %evl)
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ret bfloat %s
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}
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define bfloat @vpreduce_fmax_nnan_nxv4f16(bfloat %start, <vscale x 4 x bfloat> %val, <vscale x 4 x i1> %m, i32 zeroext %evl) {
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; CHECK-LABEL: vpreduce_fmax_nnan_nxv4f16:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma
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; CHECK-NEXT: vfwcvtbf16.f.f.v v10, v8
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; CHECK-NEXT: fcvt.s.bf16 fa5, fa0
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; CHECK-NEXT: vsetivli zero, 1, e32, m2, ta, ma
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; CHECK-NEXT: vfmv.s.f v8, fa5
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; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma
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; CHECK-NEXT: vfredmax.vs v8, v10, v8, v0.t
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; CHECK-NEXT: vfmv.f.s fa5, v8
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; CHECK-NEXT: fcvt.bf16.s fa0, fa5
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; CHECK-NEXT: ret
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%s = call nnan bfloat @llvm.vp.reduce.fmax.nxv4f16(bfloat %start, <vscale x 4 x bfloat> %val, <vscale x 4 x i1> %m, i32 %evl)
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ret bfloat %s
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}
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define bfloat @vpreduce_fminimum_nxv4f16(bfloat %start, <vscale x 4 x bfloat> %val, <vscale x 4 x i1> %m, i32 zeroext %evl) {
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; CHECK-LABEL: vpreduce_fminimum_nxv4f16:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma
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; CHECK-NEXT: vfwcvtbf16.f.f.v v10, v8
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; CHECK-NEXT: fcvt.s.bf16 fa5, fa0
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; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
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; CHECK-NEXT: vmfne.vv v8, v10, v10, v0.t
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; CHECK-NEXT: feq.s a1, fa5, fa5
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; CHECK-NEXT: vcpop.m a2, v8, v0.t
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; CHECK-NEXT: xori a1, a1, 1
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; CHECK-NEXT: or a1, a2, a1
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; CHECK-NEXT: beqz a1, .LBB4_2
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; CHECK-NEXT: # %bb.1:
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; CHECK-NEXT: lui a0, 523264
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; CHECK-NEXT: fmv.w.x fa5, a0
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; CHECK-NEXT: fcvt.bf16.s fa0, fa5
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; CHECK-NEXT: ret
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; CHECK-NEXT: .LBB4_2:
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; CHECK-NEXT: vsetivli zero, 1, e32, m2, ta, ma
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; CHECK-NEXT: vfmv.s.f v8, fa5
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; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma
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; CHECK-NEXT: vfredmin.vs v8, v10, v8, v0.t
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; CHECK-NEXT: vfmv.f.s fa5, v8
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; CHECK-NEXT: fcvt.bf16.s fa0, fa5
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; CHECK-NEXT: ret
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%s = call bfloat @llvm.vp.reduce.fminimum.nxv4f16(bfloat %start, <vscale x 4 x bfloat> %val, <vscale x 4 x i1> %m, i32 %evl)
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ret bfloat %s
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}
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define bfloat @vpreduce_fmaximum_nxv4f16(bfloat %start, <vscale x 4 x bfloat> %val, <vscale x 4 x i1> %m, i32 zeroext %evl) {
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; CHECK-LABEL: vpreduce_fmaximum_nxv4f16:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma
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; CHECK-NEXT: vfwcvtbf16.f.f.v v10, v8
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; CHECK-NEXT: fcvt.s.bf16 fa5, fa0
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; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma
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; CHECK-NEXT: vmfne.vv v8, v10, v10, v0.t
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; CHECK-NEXT: feq.s a1, fa5, fa5
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; CHECK-NEXT: vcpop.m a2, v8, v0.t
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; CHECK-NEXT: xori a1, a1, 1
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; CHECK-NEXT: or a1, a2, a1
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; CHECK-NEXT: beqz a1, .LBB5_2
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; CHECK-NEXT: # %bb.1:
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; CHECK-NEXT: lui a0, 523264
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; CHECK-NEXT: fmv.w.x fa5, a0
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; CHECK-NEXT: fcvt.bf16.s fa0, fa5
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; CHECK-NEXT: ret
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; CHECK-NEXT: .LBB5_2:
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; CHECK-NEXT: vsetivli zero, 1, e32, m2, ta, ma
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; CHECK-NEXT: vfmv.s.f v8, fa5
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; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma
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; CHECK-NEXT: vfredmax.vs v8, v10, v8, v0.t
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; CHECK-NEXT: vfmv.f.s fa5, v8
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; CHECK-NEXT: fcvt.bf16.s fa0, fa5
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; CHECK-NEXT: ret
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%s = call bfloat @llvm.vp.reduce.fmaximum.nxv4f16(bfloat %start, <vscale x 4 x bfloat> %val, <vscale x 4 x i1> %m, i32 %evl)
132+
ret bfloat %s
133+
}
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define bfloat @vpreduce_fminimum_nnan_nxv4f16(bfloat %start, <vscale x 4 x bfloat> %val, <vscale x 4 x i1> %m, i32 zeroext %evl) {
136+
; CHECK-LABEL: vpreduce_fminimum_nnan_nxv4f16:
137+
; CHECK: # %bb.0:
138+
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma
139+
; CHECK-NEXT: vfwcvtbf16.f.f.v v10, v8
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; CHECK-NEXT: fcvt.s.bf16 fa5, fa0
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; CHECK-NEXT: vsetivli zero, 1, e32, m2, ta, ma
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; CHECK-NEXT: vfmv.s.f v8, fa5
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; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma
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; CHECK-NEXT: vfredmin.vs v8, v10, v8, v0.t
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; CHECK-NEXT: vfmv.f.s fa5, v8
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; CHECK-NEXT: fcvt.bf16.s fa0, fa5
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; CHECK-NEXT: ret
148+
%s = call nnan bfloat @llvm.vp.reduce.fminimum.nxv4f16(bfloat %start, <vscale x 4 x bfloat> %val, <vscale x 4 x i1> %m, i32 %evl)
149+
ret bfloat %s
150+
}
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define bfloat @vpreduce_fmaximum_nnan_nxv4f16(bfloat %start, <vscale x 4 x bfloat> %val, <vscale x 4 x i1> %m, i32 zeroext %evl) {
153+
; CHECK-LABEL: vpreduce_fmaximum_nnan_nxv4f16:
154+
; CHECK: # %bb.0:
155+
; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma
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; CHECK-NEXT: vfwcvtbf16.f.f.v v10, v8
157+
; CHECK-NEXT: fcvt.s.bf16 fa5, fa0
158+
; CHECK-NEXT: vsetivli zero, 1, e32, m2, ta, ma
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; CHECK-NEXT: vfmv.s.f v8, fa5
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; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma
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; CHECK-NEXT: vfredmax.vs v8, v10, v8, v0.t
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; CHECK-NEXT: vfmv.f.s fa5, v8
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; CHECK-NEXT: fcvt.bf16.s fa0, fa5
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; CHECK-NEXT: ret
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%s = call nnan bfloat @llvm.vp.reduce.fmaximum.nxv4f16(bfloat %start, <vscale x 4 x bfloat> %val, <vscale x 4 x i1> %m, i32 %evl)
166+
ret bfloat %s
167+
}

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