We read every piece of feedback, and take your input very seriously.
To see all available qualifiers, see our documentation.
There was an error while loading. Please reload this page.
1 parent 9240f37 commit 23f2074Copy full SHA for 23f2074
llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
@@ -1698,7 +1698,7 @@ void RISCVInsertVSETVLI::coalesceVSETVLIs(MachineBasicBlock &MBB) const {
1698
MI.getOperand(0).setReg(DefReg);
1699
MI.getOperand(0).setIsDead(false);
1700
1701
- // Move the AVL from MI to NextMI
+ // Move the AVL from NextMI to MI
1702
dropAVLUse(MI.getOperand(1));
1703
if (NextMI->getOperand(1).isImm())
1704
MI.getOperand(1).ChangeToImmediate(NextMI->getOperand(1).getImm());
0 commit comments