[gn build] Port 03847f1

Author: llvmgnsyncbot

llvm/utils/gn/secondary/llvm/lib/Target/AMDGPU/BUILD.gn

@@ -187,6 +187,7 @@ static_library("LLVMAMDGPUCodeGen") {
     "AMDGPUResourceUsageAnalysis.cpp",
     "AMDGPURewriteOutArguments.cpp",
     "AMDGPURewriteUndefForPHI.cpp",
+    "AMDGPUSelectionDAGInfo.cpp",
     "AMDGPUSetWavePriority.cpp",
     "AMDGPUSplitModule.cpp",
     "AMDGPUSubtarget.cpp",

llvm/utils/gn/secondary/llvm/lib/Target/Mips/BUILD.gn

@@ -108,6 +108,7 @@ static_library("LLVMMipsCodeGen") {
     "MipsSEISelLowering.cpp",
     "MipsSEInstrInfo.cpp",
     "MipsSERegisterInfo.cpp",
+    "MipsSelectionDAGInfo.cpp",
     "MipsSubtarget.cpp",
     "MipsTargetMachine.cpp",
     "MipsTargetObjectFile.cpp",

llvm/utils/gn/secondary/llvm/lib/Target/NVPTX/BUILD.gn

@@ -50,6 +50,7 @@ static_library("LLVMNVPTXCodeGen") {
     "NVPTXProxyRegErasure.cpp",
     "NVPTXRegisterInfo.cpp",
     "NVPTXReplaceImageHandles.cpp",
+    "NVPTXSelectionDAGInfo.cpp",
     "NVPTXSubtarget.cpp",
     "NVPTXTargetMachine.cpp",
     "NVPTXTargetTransformInfo.cpp",

llvm/utils/gn/secondary/llvm/lib/Target/PowerPC/BUILD.gn

@@ -86,6 +86,7 @@ static_library("LLVMPowerPCCodeGen") {
     "PPCPreEmitPeephole.cpp",
     "PPCReduceCRLogicals.cpp",
     "PPCRegisterInfo.cpp",
+    "PPCSelectionDAGInfo.cpp",
     "PPCSubtarget.cpp",
     "PPCTLSDynamicCall.cpp",
     "PPCTOCRegDeps.cpp",

llvm/utils/gn/secondary/llvm/lib/Target/RISCV/BUILD.gn

@@ -137,6 +137,7 @@ static_library("LLVMRISCVCodeGen") {
     "RISCVPushPopOptimizer.cpp",
     "RISCVRedundantCopyElimination.cpp",
     "RISCVRegisterInfo.cpp",
+    "RISCVSelectionDAGInfo.cpp",
     "RISCVSubtarget.cpp",
     "RISCVTargetMachine.cpp",
     "RISCVTargetObjectFile.cpp",