Skip to content

Commit 246f137

Browse files
ppenzinantonblanchard
ppenzin
and
antonblanchard
committed
[RISCV] Add TT-Ascalon-d8 processor
Ascalon is an out-of-order CPU core from Tenstorrent. Overview: https://tenstorrent.com/ip/tt-ascalon Adding 8-wide version, -mcpu=tt-ascalon-d8. Scheduling model will be added in a separate PR. Co-authored-by: Anton Blanchard <[email protected]>
1 parent 76f993b commit 246f137

File tree

4 files changed

+105
-0
lines changed

4 files changed

+105
-0
lines changed

‎clang/test/Driver/riscv-cpus.c‎

Lines changed: 54 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -104,6 +104,60 @@
104104
// RUN: %clang --target=riscv32 -### -c %s 2>&1 -mtune=syntacore-scr1-max | FileCheck -check-prefix=MTUNE-SYNTACORE-SCR1-MAX %s
105105
// MTUNE-SYNTACORE-SCR1-MAX: "-tune-cpu" "syntacore-scr1-max"
106106

107+
// RUN: %clang --target=riscv64 -### -c %s 2>&1 -mtune=tt-ascalon-d8 | FileCheck -check-prefix=MTUNE-TT-ASCALON-D8 %s
108+
// MTUNE-TT-ASCALON-D8: "-tune-cpu" "tt-ascalon-d8"
109+
110+
// RUN: %clang --target=riscv64 -### -c %s 2>&1 -mcpu=tt-ascalon-d8 | FileCheck -check-prefix=MCPU-TT-ASCALON-D8 %s
111+
// MCPU-TT-ASCALON-D8: "-target-cpu" "tt-ascalon-d8"
112+
// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+m" "-target-feature" "+a"
113+
// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+f" "-target-feature" "+d"
114+
// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+c" "-target-feature" "+v"
115+
// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+h" "-target-feature" "+zicbom"
116+
// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zicbop"
117+
// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zicboz"
118+
// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zicntr"
119+
// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zicond"
120+
// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zicsr"
121+
// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zifencei"
122+
// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zihintntl"
123+
// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zihintpause"
124+
// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zihpm"
125+
// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zmmul"
126+
// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zawrs"
127+
// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zfa"
128+
// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zfbfmin"
129+
// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zfh"
130+
// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zfhmin"
131+
// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zca" "-target-feature" "+zcb"
132+
// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zba" "-target-feature" "+zbb"
133+
// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zbs" "-target-feature" "+zkt"
134+
// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zvbb"
135+
// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zvbc"
136+
// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zve32f"
137+
// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zve32x"
138+
// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zve64d"
139+
// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zve64f"
140+
// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zve64x"
141+
// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zvfbfmin"
142+
// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zvfbfwma"
143+
// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zvfh"
144+
// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zvfhmin"
145+
// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zvkb"
146+
// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zvkg"
147+
// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zvkn"
148+
// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zvknc"
149+
// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zvkned"
150+
// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zvkng"
151+
// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zvknhb"
152+
// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zvkt"
153+
// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zvl128b"
154+
// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zvl256b"
155+
// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zvl32b"
156+
// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+zvl64b"
157+
// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+svinval"
158+
// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+svnapot"
159+
// MCPU-TT-ASCALON-D8-SAME: "-target-feature" "+svpbmt"
160+
107161
// RUN: %clang --target=riscv64 -### -c %s 2>&1 -mcpu=veyron-v1 | FileCheck -check-prefix=MCPU-VEYRON-V1 %s
108162
// MCPU-VEYRON-V1: "-target-cpu" "veyron-v1"
109163
// MCPU-VEYRON-V1: "-target-feature" "+m"

‎clang/test/Misc/target-invalid-cpu-note/riscv.c‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -41,6 +41,7 @@
4141
// RISCV64-SAME: {{^}}, syntacore-scr4-rv64
4242
// RISCV64-SAME: {{^}}, syntacore-scr5-rv64
4343
// RISCV64-SAME: {{^}}, syntacore-scr7
44+
// RISCV64-SAME: {{^}}, tt-ascalon-d8
4445
// RISCV64-SAME: {{^}}, veyron-v1
4546
// RISCV64-SAME: {{^}}, xiangshan-nanhu
4647
// RISCV64-SAME: {{$}}
@@ -87,6 +88,7 @@
8788
// TUNE-RISCV64-SAME: {{^}}, syntacore-scr4-rv64
8889
// TUNE-RISCV64-SAME: {{^}}, syntacore-scr5-rv64
8990
// TUNE-RISCV64-SAME: {{^}}, syntacore-scr7
91+
// TUNE-RISCV64-SAME: {{^}}, tt-ascalon-d8
9092
// TUNE-RISCV64-SAME: {{^}}, veyron-v1
9193
// TUNE-RISCV64-SAME: {{^}}, xiangshan-nanhu
9294
// TUNE-RISCV64-SAME: {{^}}, generic

‎llvm/docs/ReleaseNotes.md‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -185,6 +185,7 @@ Changes to the RISC-V Backend
185185
* The `Zvbc32e` and `Zvkgs` extensions are now supported experimentally.
186186
* Added `Smctr`, `Ssctr` and `Svvptc` extensions.
187187
* `-mcpu=syntacore-scr7` was added.
188+
* `-mcpu=tt-ascalon-d8` was added.
188189
* The `Zacas` extension is no longer marked as experimental.
189190
* The `Smmpm`, `Smnpm`, `Ssnpm`, `Supm`, and `Sspm` pointer masking extensions
190191
are no longer marked as experimental.

‎llvm/lib/Target/RISCV/RISCVProcessors.td‎

Lines changed: 48 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -407,6 +407,54 @@ def SYNTACORE_SCR7 : RISCVProcessorModel<"syntacore-scr7",
407407
FeatureStdExtZkn],
408408
[TuneNoDefaultUnroll, FeaturePostRAScheduler]>;
409409

410+
def TENSTORRENT_ASCALON_D8 : RISCVProcessorModel<"tt-ascalon-d8",
411+
NoSchedModel,
412+
[Feature64Bit,
413+
FeatureStdExtI,
414+
FeatureStdExtZifencei,
415+
FeatureStdExtZicsr,
416+
FeatureStdExtZicntr,
417+
FeatureStdExtZihpm,
418+
FeatureStdExtZihintpause,
419+
FeatureStdExtM,
420+
FeatureStdExtA,
421+
FeatureStdExtF,
422+
FeatureStdExtD,
423+
FeatureStdExtC,
424+
FeatureStdExtV,
425+
FeatureStdExtZvl256b,
426+
FeatureStdExtZfh,
427+
FeatureStdExtZvfh,
428+
FeatureStdExtZba,
429+
FeatureStdExtZbb,
430+
FeatureStdExtZbs,
431+
FeatureStdExtZicbom,
432+
FeatureStdExtZicbop,
433+
FeatureStdExtZicboz,
434+
FeatureStdExtH,
435+
FeatureStdExtZihintntl,
436+
FeatureStdExtZfhmin,
437+
FeatureStdExtZfa,
438+
FeatureStdExtZkt,
439+
FeatureStdExtZcb,
440+
FeatureStdExtZvbb,
441+
FeatureStdExtZvbc,
442+
FeatureStdExtZawrs,
443+
FeatureStdExtZvkng,
444+
FeatureStdExtZicond,
445+
FeatureUnalignedScalarMem,
446+
FeatureUnalignedVectorMem,
447+
FeatureStdExtSvnapot,
448+
FeatureStdExtSvpbmt,
449+
FeatureStdExtSvinval,
450+
FeatureStdExtZfbfmin,
451+
FeatureStdExtZvfbfmin,
452+
FeatureStdExtZvfbfwma],
453+
[TuneNoDefaultUnroll,
454+
TuneOptimizedZeroStrideLoad,
455+
TuneNoSinkSplatOperands,
456+
FeaturePostRAScheduler]>;
457+
410458
def VENTANA_VEYRON_V1 : RISCVProcessorModel<"veyron-v1",
411459
NoSchedModel,
412460
[Feature64Bit,

0 commit comments

Comments
 (0)