@@ -595,10 +595,10 @@ class SIInsertWaitcnts {
595595// "s_waitcnt 0" before use.
596596class WaitcntBrackets {
597597public:
598- WaitcntBrackets (const SIInsertWaitcnts *Parent ) : Parent(Parent ) {}
598+ WaitcntBrackets (const SIInsertWaitcnts *Context ) : Context(Context ) {}
599599
600600 bool isSmemCounter (InstCounterType T) const {
601- return T == Parent ->SmemAccessCounter || T == X_CNT;
601+ return T == Context ->SmemAccessCounter || T == X_CNT;
602602 }
603603
604604 unsigned getSgprScoresIdx (InstCounterType T) const {
@@ -656,7 +656,7 @@ class WaitcntBrackets {
656656 return PendingEvents & (1 << E);
657657 }
658658 unsigned hasPendingEvent (InstCounterType T) const {
659- unsigned HasPending = PendingEvents & Parent ->WaitEventMaskForInst [T];
659+ unsigned HasPending = PendingEvents & Context ->WaitEventMaskForInst [T];
660660 assert ((HasPending != 0 ) == (getScoreRange (T) != 0 ));
661661 return HasPending;
662662 }
@@ -685,7 +685,7 @@ class WaitcntBrackets {
685685
686686 unsigned getPendingGDSWait () const {
687687 return std::min (getScoreUB (DS_CNT) - LastGDS,
688- Parent ->getWaitCountMax (DS_CNT) - 1 );
688+ Context ->getWaitCountMax (DS_CNT) - 1 );
689689 }
690690
691691 void setPendingGDS () { LastGDS = ScoreUBs[DS_CNT]; }
@@ -710,8 +710,8 @@ class WaitcntBrackets {
710710
711711 void setStateOnFunctionEntryOrReturn () {
712712 setScoreUB (STORE_CNT,
713- getScoreUB (STORE_CNT) + Parent ->getWaitCountMax (STORE_CNT));
714- PendingEvents |= Parent ->WaitEventMaskForInst [STORE_CNT];
713+ getScoreUB (STORE_CNT) + Context ->getWaitCountMax (STORE_CNT));
714+ PendingEvents |= Context ->WaitEventMaskForInst [STORE_CNT];
715715 }
716716
717717 ArrayRef<const MachineInstr *> getLDSDMAStores () const {
@@ -747,8 +747,8 @@ class WaitcntBrackets {
747747 if (T != EXP_CNT)
748748 return ;
749749
750- if (getScoreRange (EXP_CNT) > Parent ->getWaitCountMax (EXP_CNT))
751- ScoreLBs[EXP_CNT] = ScoreUBs[EXP_CNT] - Parent ->getWaitCountMax (EXP_CNT);
750+ if (getScoreRange (EXP_CNT) > Context ->getWaitCountMax (EXP_CNT))
751+ ScoreLBs[EXP_CNT] = ScoreUBs[EXP_CNT] - Context ->getWaitCountMax (EXP_CNT);
752752 }
753753
754754 void setRegScore (int GprNo, InstCounterType T, unsigned Val) {
@@ -763,7 +763,7 @@ class WaitcntBrackets {
763763 const MachineOperand &Op, InstCounterType CntTy,
764764 unsigned Val);
765765
766- const SIInsertWaitcnts *Parent ;
766+ const SIInsertWaitcnts *Context ;
767767
768768 unsigned ScoreLBs[NUM_INST_CNTS] = {0 };
769769 unsigned ScoreUBs[NUM_INST_CNTS] = {0 };
@@ -826,7 +826,7 @@ RegInterval WaitcntBrackets::getRegInterval(const MachineInstr *MI,
826826
827827 RegInterval Result;
828828
829- MCRegister MCReg = AMDGPU::getMCReg (Op.getReg (), *Parent ->ST );
829+ MCRegister MCReg = AMDGPU::getMCReg (Op.getReg (), *Context ->ST );
830830 unsigned RegIdx = TRI->getHWRegIndex (MCReg);
831831 assert (isUInt<8 >(RegIdx));
832832
@@ -884,7 +884,7 @@ void WaitcntBrackets::setScoreByOperand(const MachineInstr *MI,
884884// this at compile time, so we have to assume it might be applied if the
885885// instruction supports it).
886886bool WaitcntBrackets::hasPointSampleAccel (const MachineInstr &MI) const {
887- if (!Parent ->ST ->hasPointSampleAccel () || !SIInstrInfo::isMIMG (MI))
887+ if (!Context ->ST ->hasPointSampleAccel () || !SIInstrInfo::isMIMG (MI))
888888 return false ;
889889
890890 const AMDGPU::MIMGInfo *Info = AMDGPU::getMIMGInfo (MI.getOpcode ());
@@ -910,7 +910,7 @@ void WaitcntBrackets::updateByEvent(const SIInstrInfo *TII,
910910 const SIRegisterInfo *TRI,
911911 const MachineRegisterInfo *MRI,
912912 WaitEventType E, MachineInstr &Inst) {
913- InstCounterType T = eventCounter (Parent ->WaitEventMaskForInst , E);
913+ InstCounterType T = eventCounter (Context ->WaitEventMaskForInst , E);
914914
915915 unsigned UB = getScoreUB (T);
916916 unsigned CurrScore = UB + 1 ;
@@ -1079,10 +1079,10 @@ void WaitcntBrackets::updateByEvent(const SIInstrInfo *TII,
10791079}
10801080
10811081void WaitcntBrackets::print (raw_ostream &OS) const {
1082- const GCNSubtarget *ST = Parent ->ST ;
1082+ const GCNSubtarget *ST = Context ->ST ;
10831083
10841084 OS << ' \n ' ;
1085- for (auto T : inst_counter_types (Parent ->MaxCounter )) {
1085+ for (auto T : inst_counter_types (Context ->MaxCounter )) {
10861086 unsigned SR = getScoreRange (T);
10871087
10881088 switch (T) {
@@ -1196,7 +1196,7 @@ void WaitcntBrackets::determineWait(InstCounterType T, RegInterval Interval,
11961196 // s_waitcnt instruction.
11971197 if ((UB >= ScoreToWait) && (ScoreToWait > LB)) {
11981198 if ((T == LOAD_CNT || T == DS_CNT) && hasPendingFlat () &&
1199- !Parent ->ST ->hasFlatLgkmVMemCountInOrder ()) {
1199+ !Context ->ST ->hasFlatLgkmVMemCountInOrder ()) {
12001200 // If there is a pending FLAT operation, and this is a VMem or LGKM
12011201 // waitcnt and the target can report early completion, then we need
12021202 // to force a waitcnt 0.
@@ -1210,7 +1210,7 @@ void WaitcntBrackets::determineWait(InstCounterType T, RegInterval Interval,
12101210 // If a counter has been maxed out avoid overflow by waiting for
12111211 // MAX(CounterType) - 1 instead.
12121212 unsigned NeededWait =
1213- std::min (UB - ScoreToWait, Parent ->getWaitCountMax (T) - 1 );
1213+ std::min (UB - ScoreToWait, Context ->getWaitCountMax (T) - 1 );
12141214 addWait (Wait, T, NeededWait);
12151215 }
12161216 }
@@ -1238,7 +1238,7 @@ void WaitcntBrackets::applyWaitcnt(InstCounterType T, unsigned Count) {
12381238 setScoreLB (T, std::max (getScoreLB (T), UB - Count));
12391239 } else {
12401240 setScoreLB (T, UB);
1241- PendingEvents &= ~Parent ->WaitEventMaskForInst [T];
1241+ PendingEvents &= ~Context ->WaitEventMaskForInst [T];
12421242 }
12431243}
12441244
@@ -1263,7 +1263,7 @@ void WaitcntBrackets::applyXcnt(const AMDGPU::Waitcnt &Wait) {
12631263// the decrement may go out of order.
12641264bool WaitcntBrackets::counterOutOfOrder (InstCounterType T) const {
12651265 // Scalar memory read always can go out of order.
1266- if ((T == Parent ->SmemAccessCounter && hasPendingEvent (SMEM_ACCESS)) ||
1266+ if ((T == Context ->SmemAccessCounter && hasPendingEvent (SMEM_ACCESS)) ||
12671267 (T == X_CNT && hasPendingEvent (SMEM_GROUP)))
12681268 return true ;
12691269 return hasMixedPendingEvents (T);
@@ -2387,9 +2387,9 @@ bool WaitcntBrackets::merge(const WaitcntBrackets &Other) {
23872387 VgprUB = std::max (VgprUB, Other.VgprUB );
23882388 SgprUB = std::max (SgprUB, Other.SgprUB );
23892389
2390- for (auto T : inst_counter_types (Parent ->MaxCounter )) {
2390+ for (auto T : inst_counter_types (Context ->MaxCounter )) {
23912391 // Merge event flags for this counter
2392- const unsigned *WaitEventMaskForInst = Parent ->WaitEventMaskForInst ;
2392+ const unsigned *WaitEventMaskForInst = Context ->WaitEventMaskForInst ;
23932393 const unsigned OldEvents = PendingEvents & WaitEventMaskForInst[T];
23942394 const unsigned OtherEvents = Other.PendingEvents & WaitEventMaskForInst[T];
23952395 if (OtherEvents & ~OldEvents)
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