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[InstCombine] Fold min(X+1, Y) - min(X, Y) --> zext X < Y (#157782)
This PR closes #157524. alive2: https://alive2.llvm.org/ce/z/xe_vb2 godbolt: https://alive2.llvm.org/ce/z/7A8PxK This fold is invalid for `@llvm.smin.i1` since `smin(-1, 0) == -1`. I also avoided i1 in general since this uses zext, but it seems like those checks for width might not be necessary, since other folds get to it first. The alive2 proof in #157524 used a select for the fold, but it seems like `select X < Y, 1, 0` should be canonicalized to `zext X < Y` if the bit width is correct.
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‎llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp‎

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@@ -2731,6 +2731,24 @@ Instruction *InstCombinerImpl::visitSub(BinaryOperator &I) {
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return BinaryOperator::CreateSub(X, Not);
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}
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// min(X+1, Y) - min(X, Y) --> zext X < Y
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// Replacing a sub and at least one min with an icmp
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// and a zext is a potential improvement.
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if (match(Op0, m_c_SMin(m_NSWAddLike(m_Value(X), m_One()), m_Value(Y))) &&
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match(Op1, m_c_SMin(m_Specific(X), m_Specific(Y))) &&
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I.getType()->getScalarSizeInBits() != 1 &&
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(Op0->hasOneUse() || Op1->hasOneUse())) {
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Value *Cond = Builder.CreateICmpSLT(X, Y);
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return new ZExtInst(Cond, I.getType());
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}
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if (match(Op0, m_c_UMin(m_NUWAddLike(m_Value(X), m_One()), m_Value(Y))) &&
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match(Op1, m_c_UMin(m_Specific(X), m_Specific(Y))) &&
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I.getType()->getScalarSizeInBits() != 1 &&
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(Op0->hasOneUse() || Op1->hasOneUse())) {
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Value *Cond = Builder.CreateICmpULT(X, Y);
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return new ZExtInst(Cond, I.getType());
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}
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// Optimize pointer differences into the same array into a size. Consider:
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// &A[10] - &A[0]: we should compile this to "10".
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Value *LHSOp, *RHSOp;

‎llvm/test/Transforms/InstCombine/min-zext.ll‎

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; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 6
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; RUN: opt < %s -passes=instcombine -S | FileCheck %s
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define i32 @test_smin(i32 %arg0, i32 %arg1) {
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; CHECK-LABEL: define i32 @test_smin(
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; CHECK-SAME: i32 [[ARG0:%.*]], i32 [[ARG1:%.*]]) {
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; CHECK-NEXT: [[TMP1:%.*]] = icmp slt i32 [[ARG0]], [[ARG1]]
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; CHECK-NEXT: [[V3:%.*]] = zext i1 [[TMP1]] to i32
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; CHECK-NEXT: ret i32 [[V3]]
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;
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%v0 = tail call i32 @llvm.smin.i32(i32 %arg0, i32 %arg1)
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%v1 = add nsw i32 %arg0, 1
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%v2 = tail call i32 @llvm.smin.i32(i32 %v1, i32 %arg1)
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%v3 = sub i32 %v2, %v0
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ret i32 %v3
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}
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define i32 @test_umin(i32 %arg0, i32 %arg1) {
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; CHECK-LABEL: define i32 @test_umin(
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; CHECK-SAME: i32 [[ARG0:%.*]], i32 [[ARG1:%.*]]) {
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; CHECK-NEXT: [[TMP1:%.*]] = icmp ult i32 [[ARG0]], [[ARG1]]
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; CHECK-NEXT: [[V3:%.*]] = zext i1 [[TMP1]] to i32
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; CHECK-NEXT: ret i32 [[V3]]
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;
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%v0 = tail call i32 @llvm.umin.i32(i32 %arg0, i32 %arg1)
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%v1 = add nuw i32 %arg0, 1
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%v2 = tail call i32 @llvm.umin.i32(i32 %v1, i32 %arg1)
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%v3 = sub i32 %v2, %v0
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ret i32 %v3
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}
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define i1 @test_smin_i1(i1 %arg0, i1 %arg1) {
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; CHECK-LABEL: define i1 @test_smin_i1(
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; CHECK-SAME: i1 [[ARG0:%.*]], i1 [[ARG1:%.*]]) {
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; CHECK-NEXT: [[V0:%.*]] = or i1 [[ARG0]], [[ARG1]]
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; CHECK-NEXT: [[V3:%.*]] = xor i1 [[V0]], true
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; CHECK-NEXT: ret i1 [[V3]]
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;
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%v0 = tail call i1 @llvm.smin.i1(i1 %arg0, i1 %arg1)
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%v1 = add nsw i1 %arg0, 1
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%v2 = tail call i1 @llvm.smin.i1(i1 %v1, i1 %arg1)
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%v3 = sub i1 %v2, %v0
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ret i1 %v3
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}
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declare void @use(i2)
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define i2 @test_smin_use_operands(i2 %arg0, i2 %arg1) {
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; CHECK-LABEL: define i2 @test_smin_use_operands(
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; CHECK-SAME: i2 [[ARG0:%.*]], i2 [[ARG1:%.*]]) {
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; CHECK-NEXT: [[V0:%.*]] = tail call i2 @llvm.smin.i2(i2 [[ARG0]], i2 [[ARG1]])
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; CHECK-NEXT: [[V1:%.*]] = add nsw i2 [[ARG0]], 1
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; CHECK-NEXT: [[V2:%.*]] = tail call i2 @llvm.smin.i2(i2 [[V1]], i2 [[ARG1]])
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; CHECK-NEXT: [[V3:%.*]] = sub i2 [[V2]], [[V0]]
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; CHECK-NEXT: call void @use(i2 [[V2]])
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; CHECK-NEXT: call void @use(i2 [[V0]])
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; CHECK-NEXT: ret i2 [[V3]]
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;
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%v0 = tail call i2 @llvm.smin.i2(i2 %arg0, i2 %arg1)
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%v1 = add nsw i2 %arg0, 1
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%v2 = tail call i2 @llvm.smin.i2(i2 %v1, i2 %arg1)
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%v3 = sub i2 %v2, %v0
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call void @use(i2 %v2)
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call void @use(i2 %v0)
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ret i2 %v3
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}
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define i2 @test_smin_use_operand(i2 %arg0, i2 %arg1) {
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; CHECK-LABEL: define i2 @test_smin_use_operand(
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; CHECK-SAME: i2 [[ARG0:%.*]], i2 [[ARG1:%.*]]) {
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; CHECK-NEXT: [[V1:%.*]] = add nsw i2 [[ARG0]], 1
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; CHECK-NEXT: [[V2:%.*]] = tail call i2 @llvm.smin.i2(i2 [[V1]], i2 [[ARG1]])
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; CHECK-NEXT: [[TMP1:%.*]] = icmp slt i2 [[ARG0]], [[ARG1]]
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; CHECK-NEXT: [[V3:%.*]] = zext i1 [[TMP1]] to i2
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; CHECK-NEXT: call void @use(i2 [[V2]])
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; CHECK-NEXT: ret i2 [[V3]]
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;
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%v0 = tail call i2 @llvm.smin.i2(i2 %arg0, i2 %arg1)
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%v1 = add nsw i2 %arg0, 1
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%v2 = tail call i2 @llvm.smin.i2(i2 %v1, i2 %arg1)
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%v3 = sub i2 %v2, %v0
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call void @use(i2 %v2)
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ret i2 %v3
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}
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define i32 @test_smin_missing_nsw(i32 %arg0, i32 %arg1) {
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; CHECK-LABEL: define i32 @test_smin_missing_nsw(
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; CHECK-SAME: i32 [[ARG0:%.*]], i32 [[ARG1:%.*]]) {
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; CHECK-NEXT: [[V0:%.*]] = tail call i32 @llvm.smin.i32(i32 [[ARG0]], i32 [[ARG1]])
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; CHECK-NEXT: [[V1:%.*]] = add i32 [[ARG0]], 1
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; CHECK-NEXT: [[V2:%.*]] = tail call i32 @llvm.smin.i32(i32 [[V1]], i32 [[ARG1]])
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; CHECK-NEXT: [[V3:%.*]] = sub i32 [[V2]], [[V0]]
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; CHECK-NEXT: ret i32 [[V3]]
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;
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%v0 = tail call i32 @llvm.smin.i32(i32 %arg0, i32 %arg1)
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%v1 = add i32 %arg0, 1
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%v2 = tail call i32 @llvm.smin.i32(i32 %v1, i32 %arg1)
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%v3 = sub i32 %v2, %v0
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ret i32 %v3
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}
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define i32 @test_umin_missing_nuw(i32 %arg0, i32 %arg1) {
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; CHECK-LABEL: define i32 @test_umin_missing_nuw(
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; CHECK-SAME: i32 [[ARG0:%.*]], i32 [[ARG1:%.*]]) {
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; CHECK-NEXT: [[V0:%.*]] = tail call i32 @llvm.umin.i32(i32 [[ARG0]], i32 [[ARG1]])
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; CHECK-NEXT: [[V1:%.*]] = add i32 [[ARG0]], 1
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; CHECK-NEXT: [[V2:%.*]] = tail call i32 @llvm.umin.i32(i32 [[V1]], i32 [[ARG1]])
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; CHECK-NEXT: [[V3:%.*]] = sub i32 [[V2]], [[V0]]
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; CHECK-NEXT: ret i32 [[V3]]
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;
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%v0 = tail call i32 @llvm.umin.i32(i32 %arg0, i32 %arg1)
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%v1 = add i32 %arg0, 1
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%v2 = tail call i32 @llvm.umin.i32(i32 %v1, i32 %arg1)
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%v3 = sub i32 %v2, %v0
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ret i32 %v3
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}
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@tmp = external global i32
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define i32 @test_mismatched_operands(i32 %arg0, i32 %arg1) {
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; CHECK-LABEL: define i32 @test_mismatched_operands(
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; CHECK-SAME: i32 [[ARG0:%.*]], i32 [[ARG1:%.*]]) {
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; CHECK-NEXT: [[TMP:%.*]] = load i32, ptr @tmp, align 4
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; CHECK-NEXT: [[V0:%.*]] = tail call i32 @llvm.smin.i32(i32 [[ARG0]], i32 [[TMP]])
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; CHECK-NEXT: [[V1:%.*]] = add nsw i32 [[ARG0]], 1
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; CHECK-NEXT: [[V2:%.*]] = tail call i32 @llvm.smin.i32(i32 [[V1]], i32 [[ARG1]])
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; CHECK-NEXT: [[V3:%.*]] = sub i32 [[V2]], [[V0]]
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; CHECK-NEXT: ret i32 [[V3]]
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;
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%tmp = load i32, ptr @tmp, align 4
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%v0 = tail call i32 @llvm.smin.i32(i32 %arg0, i32 %tmp)
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%v1 = add nsw i32 %arg0, 1
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%v2 = tail call i32 @llvm.smin.i32(i32 %v1, i32 %arg1)
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%v3 = sub i32 %v2, %v0
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ret i32 %v3
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}
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define i32 @test_disjoint_or(i32 %arg0, i32 %arg1) {
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; CHECK-LABEL: define i32 @test_disjoint_or(
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; CHECK-SAME: i32 [[ARG0:%.*]], i32 [[ARG1:%.*]]) {
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; CHECK-NEXT: [[TMP1:%.*]] = icmp slt i32 [[ARG0]], [[ARG1]]
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; CHECK-NEXT: [[V3:%.*]] = zext i1 [[TMP1]] to i32
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; CHECK-NEXT: ret i32 [[V3]]
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;
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%v0 = tail call i32 @llvm.smin.i32(i32 %arg0, i32 %arg1)
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%v1 = or disjoint i32 %arg0, 1
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%v2 = tail call i32 @llvm.smin.i32(i32 %v1, i32 %arg1)
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%v3 = sub i32 %v2, %v0
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ret i32 %v3
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}

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