Skip to content

Commit 2519013

Browse files
vladimirradosavljevicvladimirradosavljevic
committed
[MCP] Optimize copies when src is used during backward propagation
Before this patch, redundant COPY couldn't be removed for the following case: $R0 = OP ... ... // Read of %R0 $R1 = COPY killed $R0 This patch adds support for tracking the users of the source register during backward propagation, so that we can remove the redundant COPY in the above case and optimize it to: $R1 = OP ... ... // Replace all uses of %R0 with $R1
1 parent a3a253d commit 2519013

File tree

65 files changed

+4383
-5939
lines changed

Some content is hidden

Large Commits have some content hidden by default. Use the searchbox below for content that may be hidden.

65 files changed

+4383
-5939
lines changed

‎llvm/lib/CodeGen/MachineCopyPropagation.cpp‎

Lines changed: 76 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -110,6 +110,7 @@ class CopyTracker {
110110
struct CopyInfo {
111111
MachineInstr *MI = nullptr;
112112
MachineInstr *LastSeenUseInCopy = nullptr;
113+
SmallPtrSet<MachineInstr *, 4> SrcUsers;
113114
SmallVector<MCRegister, 4> DefRegs;
114115
bool Avail = false;
115116
};
@@ -224,6 +225,43 @@ class CopyTracker {
224225
}
225226
}
226227

228+
/// Track copy's src users, and return false if that can't be done.
229+
/// We can only track if we have a COPY instruction which source is
230+
/// the same as the Reg.
231+
bool trackSrcUsers(MCRegister Reg, MachineInstr &MI,
232+
const TargetRegisterInfo &TRI, const TargetInstrInfo &TII,
233+
bool UseCopyInstr) {
234+
MCRegUnit RU = *TRI.regunits(Reg).begin();
235+
MachineInstr *AvailCopy = findCopyDefViaUnit(RU, TRI);
236+
if (!AvailCopy)
237+
return false;
238+
239+
std::optional<DestSourcePair> CopyOperands =
240+
isCopyInstr(*AvailCopy, TII, UseCopyInstr);
241+
Register Src = CopyOperands->Source->getReg();
242+
243+
// Bail out, if the source of the copy is not the same as the Reg.
244+
if (Src != Reg)
245+
return false;
246+
247+
auto I = Copies.find(RU);
248+
if (I == Copies.end())
249+
return false;
250+
251+
I->second.SrcUsers.insert(&MI);
252+
return true;
253+
}
254+
255+
/// Return the users for a given register.
256+
SmallPtrSet<MachineInstr *, 4> getSrcUsers(MCRegister Reg,
257+
const TargetRegisterInfo &TRI) {
258+
MCRegUnit RU = *TRI.regunits(Reg).begin();
259+
auto I = Copies.find(RU);
260+
if (I == Copies.end())
261+
return {};
262+
return I->second.SrcUsers;
263+
}
264+
227265
/// Add this copy's registers into the tracker's copy maps.
228266
void trackCopy(MachineInstr *MI, const TargetRegisterInfo &TRI,
229267
const TargetInstrInfo &TII, bool UseCopyInstr) {
@@ -236,7 +274,7 @@ class CopyTracker {
236274

237275
// Remember Def is defined by the copy.
238276
for (MCRegUnit Unit : TRI.regunits(Def))
239-
Copies[Unit] = {MI, nullptr, {}, true};
277+
Copies[Unit] = {MI, nullptr, {}, {}, true};
240278

241279
// Remember source that's copied to Def. Once it's clobbered, then
242280
// it's no longer available for copy propagation.
@@ -427,6 +465,8 @@ class MachineCopyPropagation : public MachineFunctionPass {
427465
bool hasImplicitOverlap(const MachineInstr &MI, const MachineOperand &Use);
428466
bool hasOverlappingMultipleDef(const MachineInstr &MI,
429467
const MachineOperand &MODef, Register Def);
468+
bool canUpdateSrcUsers(const MachineInstr &Copy,
469+
const MachineOperand &CopySrc);
430470

431471
/// Candidates for deletion.
432472
SmallSetVector<MachineInstr *, 8> MaybeDeadCopies;
@@ -667,6 +707,26 @@ bool MachineCopyPropagation::hasOverlappingMultipleDef(
667707
return false;
668708
}
669709

710+
/// Return true if it is safe to update the users of the source register of the
711+
/// copy.
712+
bool MachineCopyPropagation::canUpdateSrcUsers(const MachineInstr &Copy,
713+
const MachineOperand &CopySrc) {
714+
for (auto *SrcUser : Tracker.getSrcUsers(CopySrc.getReg(), *TRI)) {
715+
if (hasImplicitOverlap(*SrcUser, CopySrc))
716+
return false;
717+
718+
for (MachineOperand &MO : SrcUser->uses()) {
719+
if (!MO.isReg() || !MO.isUse() || MO.getReg() != CopySrc.getReg())
720+
continue;
721+
if (MO.isTied() || !MO.isRenamable() ||
722+
!isBackwardPropagatableRegClassCopy(Copy, *SrcUser,
723+
MO.getOperandNo()))
724+
return false;
725+
}
726+
}
727+
return true;
728+
}
729+
670730
/// Look for available copies whose destination register is used by \p MI and
671731
/// replace the use in \p MI with the copy's source register.
672732
void MachineCopyPropagation::forwardUses(MachineInstr &MI) {
@@ -1030,13 +1090,25 @@ void MachineCopyPropagation::propagateDefs(MachineInstr &MI) {
10301090
if (hasOverlappingMultipleDef(MI, MODef, Def))
10311091
continue;
10321092

1093+
if (!canUpdateSrcUsers(*Copy, *CopyOperands->Source))
1094+
continue;
1095+
10331096
LLVM_DEBUG(dbgs() << "MCP: Replacing " << printReg(MODef.getReg(), TRI)
10341097
<< "\n with " << printReg(Def, TRI) << "\n in "
10351098
<< MI << " from " << *Copy);
10361099

10371100
MODef.setReg(Def);
10381101
MODef.setIsRenamable(CopyOperands->Destination->isRenamable());
10391102

1103+
for (auto *SrcUser : Tracker.getSrcUsers(Src, *TRI)) {
1104+
for (MachineOperand &MO : SrcUser->uses()) {
1105+
if (!MO.isReg() || !MO.isUse() || MO.getReg() != Src)
1106+
continue;
1107+
MO.setReg(Def);
1108+
MO.setIsRenamable(CopyOperands->Destination->isRenamable());
1109+
}
1110+
}
1111+
10401112
LLVM_DEBUG(dbgs() << "MCP: After replacement: " << MI << "\n");
10411113
MaybeDeadCopies.insert(Copy);
10421114
Changed = true;
@@ -1102,7 +1174,9 @@ void MachineCopyPropagation::BackwardCopyPropagateBlock(
11021174
CopyDbgUsers[Copy].insert(&MI);
11031175
}
11041176
}
1105-
} else {
1177+
} else if (!Tracker.trackSrcUsers(MO.getReg().asMCReg(), MI, *TRI, *TII,
1178+
UseCopyInstr)) {
1179+
// If we can't track the source users, invalidate the register.
11061180
Tracker.invalidateRegister(MO.getReg().asMCReg(), *TRI, *TII,
11071181
UseCopyInstr);
11081182
}

‎llvm/test/CodeGen/ARM/umulo-128-legalisation-lowering.ll‎

Lines changed: 2 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -7,12 +7,11 @@ define { i128, i8 } @muloti_test(i128 %l, i128 %r) unnamed_addr #0 {
77
; ARMV6: @ %bb.0: @ %start
88
; ARMV6-NEXT: push {r4, r5, r6, r7, r8, r9, r10, r11, lr}
99
; ARMV6-NEXT: sub sp, sp, #28
10-
; ARMV6-NEXT: ldr r7, [sp, #72]
10+
; ARMV6-NEXT: ldr lr, [sp, #72]
1111
; ARMV6-NEXT: mov r6, r0
1212
; ARMV6-NEXT: str r0, [sp, #8] @ 4-byte Spill
1313
; ARMV6-NEXT: ldr r4, [sp, #84]
14-
; ARMV6-NEXT: umull r1, r0, r2, r7
15-
; ARMV6-NEXT: mov lr, r7
14+
; ARMV6-NEXT: umull r1, r0, r2, lr
1615
; ARMV6-NEXT: umull r5, r10, r4, r2
1716
; ARMV6-NEXT: str r1, [r6]
1817
; ARMV6-NEXT: ldr r6, [sp, #80]

‎llvm/test/CodeGen/Mips/llvm-ir/sdiv.ll‎

Lines changed: 30 additions & 38 deletions
Original file line numberDiff line numberDiff line change
@@ -388,9 +388,8 @@ define signext i64 @sdiv_i64(i64 signext %a, i64 signext %b) {
388388
; MMR3-NEXT: .cfi_def_cfa_offset 24
389389
; MMR3-NEXT: sw $ra, 20($sp) # 4-byte Folded Spill
390390
; MMR3-NEXT: .cfi_offset 31, -4
391-
; MMR3-NEXT: addu $2, $2, $25
392-
; MMR3-NEXT: lw $25, %call16(__divdi3)($2)
393-
; MMR3-NEXT: move $gp, $2
391+
; MMR3-NEXT: addu $gp, $2, $25
392+
; MMR3-NEXT: lw $25, %call16(__divdi3)($gp)
394393
; MMR3-NEXT: jalr $25
395394
; MMR3-NEXT: nop
396395
; MMR3-NEXT: lw $ra, 20($sp) # 4-byte Folded Reload
@@ -405,9 +404,8 @@ define signext i64 @sdiv_i64(i64 signext %a, i64 signext %b) {
405404
; MMR6-NEXT: .cfi_def_cfa_offset 24
406405
; MMR6-NEXT: sw $ra, 20($sp) # 4-byte Folded Spill
407406
; MMR6-NEXT: .cfi_offset 31, -4
408-
; MMR6-NEXT: addu $2, $2, $25
409-
; MMR6-NEXT: lw $25, %call16(__divdi3)($2)
410-
; MMR6-NEXT: move $gp, $2
407+
; MMR6-NEXT: addu $gp, $2, $25
408+
; MMR6-NEXT: lw $25, %call16(__divdi3)($gp)
411409
; MMR6-NEXT: jalr $25
412410
; MMR6-NEXT: lw $ra, 20($sp) # 4-byte Folded Reload
413411
; MMR6-NEXT: addiu $sp, $sp, 24
@@ -549,65 +547,59 @@ define signext i128 @sdiv_i128(i128 signext %a, i128 signext %b) {
549547
; MMR3: # %bb.0: # %entry
550548
; MMR3-NEXT: lui $2, %hi(_gp_disp)
551549
; MMR3-NEXT: addiu $2, $2, %lo(_gp_disp)
552-
; MMR3-NEXT: addiusp -48
553-
; MMR3-NEXT: .cfi_def_cfa_offset 48
554-
; MMR3-NEXT: sw $ra, 44($sp) # 4-byte Folded Spill
555-
; MMR3-NEXT: swp $16, 36($sp)
550+
; MMR3-NEXT: addiusp -40
551+
; MMR3-NEXT: .cfi_def_cfa_offset 40
552+
; MMR3-NEXT: sw $ra, 36($sp) # 4-byte Folded Spill
553+
; MMR3-NEXT: sw $17, 32($sp) # 4-byte Folded Spill
556554
; MMR3-NEXT: .cfi_offset 31, -4
557555
; MMR3-NEXT: .cfi_offset 17, -8
558-
; MMR3-NEXT: .cfi_offset 16, -12
559-
; MMR3-NEXT: addu $16, $2, $25
556+
; MMR3-NEXT: addu $gp, $2, $25
560557
; MMR3-NEXT: move $1, $7
561-
; MMR3-NEXT: lw $7, 68($sp)
562-
; MMR3-NEXT: lw $17, 72($sp)
563-
; MMR3-NEXT: lw $3, 76($sp)
558+
; MMR3-NEXT: lw $7, 60($sp)
559+
; MMR3-NEXT: lw $17, 64($sp)
560+
; MMR3-NEXT: lw $3, 68($sp)
564561
; MMR3-NEXT: move $2, $sp
565562
; MMR3-NEXT: sw16 $3, 28($2)
566563
; MMR3-NEXT: sw16 $17, 24($2)
567564
; MMR3-NEXT: sw16 $7, 20($2)
568-
; MMR3-NEXT: lw $3, 64($sp)
565+
; MMR3-NEXT: lw $3, 56($sp)
569566
; MMR3-NEXT: sw16 $3, 16($2)
570-
; MMR3-NEXT: lw $25, %call16(__divti3)($16)
567+
; MMR3-NEXT: lw $25, %call16(__divti3)($gp)
571568
; MMR3-NEXT: move $7, $1
572-
; MMR3-NEXT: move $gp, $16
573569
; MMR3-NEXT: jalr $25
574570
; MMR3-NEXT: nop
575-
; MMR3-NEXT: lwp $16, 36($sp)
576-
; MMR3-NEXT: lw $ra, 44($sp) # 4-byte Folded Reload
577-
; MMR3-NEXT: addiusp 48
571+
; MMR3-NEXT: lw $17, 32($sp) # 4-byte Folded Reload
572+
; MMR3-NEXT: lw $ra, 36($sp) # 4-byte Folded Reload
573+
; MMR3-NEXT: addiusp 40
578574
; MMR3-NEXT: jrc $ra
579575
;
580576
; MMR6-LABEL: sdiv_i128:
581577
; MMR6: # %bb.0: # %entry
582578
; MMR6-NEXT: lui $2, %hi(_gp_disp)
583579
; MMR6-NEXT: addiu $2, $2, %lo(_gp_disp)
584-
; MMR6-NEXT: addiu $sp, $sp, -48
585-
; MMR6-NEXT: .cfi_def_cfa_offset 48
586-
; MMR6-NEXT: sw $ra, 44($sp) # 4-byte Folded Spill
587-
; MMR6-NEXT: sw $17, 40($sp) # 4-byte Folded Spill
588-
; MMR6-NEXT: sw $16, 36($sp) # 4-byte Folded Spill
580+
; MMR6-NEXT: addiu $sp, $sp, -40
581+
; MMR6-NEXT: .cfi_def_cfa_offset 40
582+
; MMR6-NEXT: sw $ra, 36($sp) # 4-byte Folded Spill
583+
; MMR6-NEXT: sw $17, 32($sp) # 4-byte Folded Spill
589584
; MMR6-NEXT: .cfi_offset 31, -4
590585
; MMR6-NEXT: .cfi_offset 17, -8
591-
; MMR6-NEXT: .cfi_offset 16, -12
592-
; MMR6-NEXT: addu $16, $2, $25
586+
; MMR6-NEXT: addu $gp, $2, $25
593587
; MMR6-NEXT: move $1, $7
594-
; MMR6-NEXT: lw $7, 68($sp)
595-
; MMR6-NEXT: lw $17, 72($sp)
596-
; MMR6-NEXT: lw $3, 76($sp)
588+
; MMR6-NEXT: lw $7, 60($sp)
589+
; MMR6-NEXT: lw $17, 64($sp)
590+
; MMR6-NEXT: lw $3, 68($sp)
597591
; MMR6-NEXT: move $2, $sp
598592
; MMR6-NEXT: sw16 $3, 28($2)
599593
; MMR6-NEXT: sw16 $17, 24($2)
600594
; MMR6-NEXT: sw16 $7, 20($2)
601-
; MMR6-NEXT: lw $3, 64($sp)
595+
; MMR6-NEXT: lw $3, 56($sp)
602596
; MMR6-NEXT: sw16 $3, 16($2)
603-
; MMR6-NEXT: lw $25, %call16(__divti3)($16)
597+
; MMR6-NEXT: lw $25, %call16(__divti3)($gp)
604598
; MMR6-NEXT: move $7, $1
605-
; MMR6-NEXT: move $gp, $16
606599
; MMR6-NEXT: jalr $25
607-
; MMR6-NEXT: lw $16, 36($sp) # 4-byte Folded Reload
608-
; MMR6-NEXT: lw $17, 40($sp) # 4-byte Folded Reload
609-
; MMR6-NEXT: lw $ra, 44($sp) # 4-byte Folded Reload
610-
; MMR6-NEXT: addiu $sp, $sp, 48
600+
; MMR6-NEXT: lw $17, 32($sp) # 4-byte Folded Reload
601+
; MMR6-NEXT: lw $ra, 36($sp) # 4-byte Folded Reload
602+
; MMR6-NEXT: addiu $sp, $sp, 40
611603
; MMR6-NEXT: jrc $ra
612604
entry:
613605
%r = sdiv i128 %a, %b

‎llvm/test/CodeGen/Mips/llvm-ir/srem.ll‎

Lines changed: 30 additions & 38 deletions
Original file line numberDiff line numberDiff line change
@@ -336,9 +336,8 @@ define signext i64 @srem_i64(i64 signext %a, i64 signext %b) {
336336
; MMR3-NEXT: .cfi_def_cfa_offset 24
337337
; MMR3-NEXT: sw $ra, 20($sp) # 4-byte Folded Spill
338338
; MMR3-NEXT: .cfi_offset 31, -4
339-
; MMR3-NEXT: addu $2, $2, $25
340-
; MMR3-NEXT: lw $25, %call16(__moddi3)($2)
341-
; MMR3-NEXT: move $gp, $2
339+
; MMR3-NEXT: addu $gp, $2, $25
340+
; MMR3-NEXT: lw $25, %call16(__moddi3)($gp)
342341
; MMR3-NEXT: jalr $25
343342
; MMR3-NEXT: nop
344343
; MMR3-NEXT: lw $ra, 20($sp) # 4-byte Folded Reload
@@ -353,9 +352,8 @@ define signext i64 @srem_i64(i64 signext %a, i64 signext %b) {
353352
; MMR6-NEXT: .cfi_def_cfa_offset 24
354353
; MMR6-NEXT: sw $ra, 20($sp) # 4-byte Folded Spill
355354
; MMR6-NEXT: .cfi_offset 31, -4
356-
; MMR6-NEXT: addu $2, $2, $25
357-
; MMR6-NEXT: lw $25, %call16(__moddi3)($2)
358-
; MMR6-NEXT: move $gp, $2
355+
; MMR6-NEXT: addu $gp, $2, $25
356+
; MMR6-NEXT: lw $25, %call16(__moddi3)($gp)
359357
; MMR6-NEXT: jalr $25
360358
; MMR6-NEXT: lw $ra, 20($sp) # 4-byte Folded Reload
361359
; MMR6-NEXT: addiu $sp, $sp, 24
@@ -497,65 +495,59 @@ define signext i128 @srem_i128(i128 signext %a, i128 signext %b) {
497495
; MMR3: # %bb.0: # %entry
498496
; MMR3-NEXT: lui $2, %hi(_gp_disp)
499497
; MMR3-NEXT: addiu $2, $2, %lo(_gp_disp)
500-
; MMR3-NEXT: addiusp -48
501-
; MMR3-NEXT: .cfi_def_cfa_offset 48
502-
; MMR3-NEXT: sw $ra, 44($sp) # 4-byte Folded Spill
503-
; MMR3-NEXT: swp $16, 36($sp)
498+
; MMR3-NEXT: addiusp -40
499+
; MMR3-NEXT: .cfi_def_cfa_offset 40
500+
; MMR3-NEXT: sw $ra, 36($sp) # 4-byte Folded Spill
501+
; MMR3-NEXT: sw $17, 32($sp) # 4-byte Folded Spill
504502
; MMR3-NEXT: .cfi_offset 31, -4
505503
; MMR3-NEXT: .cfi_offset 17, -8
506-
; MMR3-NEXT: .cfi_offset 16, -12
507-
; MMR3-NEXT: addu $16, $2, $25
504+
; MMR3-NEXT: addu $gp, $2, $25
508505
; MMR3-NEXT: move $1, $7
509-
; MMR3-NEXT: lw $7, 68($sp)
510-
; MMR3-NEXT: lw $17, 72($sp)
511-
; MMR3-NEXT: lw $3, 76($sp)
506+
; MMR3-NEXT: lw $7, 60($sp)
507+
; MMR3-NEXT: lw $17, 64($sp)
508+
; MMR3-NEXT: lw $3, 68($sp)
512509
; MMR3-NEXT: move $2, $sp
513510
; MMR3-NEXT: sw16 $3, 28($2)
514511
; MMR3-NEXT: sw16 $17, 24($2)
515512
; MMR3-NEXT: sw16 $7, 20($2)
516-
; MMR3-NEXT: lw $3, 64($sp)
513+
; MMR3-NEXT: lw $3, 56($sp)
517514
; MMR3-NEXT: sw16 $3, 16($2)
518-
; MMR3-NEXT: lw $25, %call16(__modti3)($16)
515+
; MMR3-NEXT: lw $25, %call16(__modti3)($gp)
519516
; MMR3-NEXT: move $7, $1
520-
; MMR3-NEXT: move $gp, $16
521517
; MMR3-NEXT: jalr $25
522518
; MMR3-NEXT: nop
523-
; MMR3-NEXT: lwp $16, 36($sp)
524-
; MMR3-NEXT: lw $ra, 44($sp) # 4-byte Folded Reload
525-
; MMR3-NEXT: addiusp 48
519+
; MMR3-NEXT: lw $17, 32($sp) # 4-byte Folded Reload
520+
; MMR3-NEXT: lw $ra, 36($sp) # 4-byte Folded Reload
521+
; MMR3-NEXT: addiusp 40
526522
; MMR3-NEXT: jrc $ra
527523
;
528524
; MMR6-LABEL: srem_i128:
529525
; MMR6: # %bb.0: # %entry
530526
; MMR6-NEXT: lui $2, %hi(_gp_disp)
531527
; MMR6-NEXT: addiu $2, $2, %lo(_gp_disp)
532-
; MMR6-NEXT: addiu $sp, $sp, -48
533-
; MMR6-NEXT: .cfi_def_cfa_offset 48
534-
; MMR6-NEXT: sw $ra, 44($sp) # 4-byte Folded Spill
535-
; MMR6-NEXT: sw $17, 40($sp) # 4-byte Folded Spill
536-
; MMR6-NEXT: sw $16, 36($sp) # 4-byte Folded Spill
528+
; MMR6-NEXT: addiu $sp, $sp, -40
529+
; MMR6-NEXT: .cfi_def_cfa_offset 40
530+
; MMR6-NEXT: sw $ra, 36($sp) # 4-byte Folded Spill
531+
; MMR6-NEXT: sw $17, 32($sp) # 4-byte Folded Spill
537532
; MMR6-NEXT: .cfi_offset 31, -4
538533
; MMR6-NEXT: .cfi_offset 17, -8
539-
; MMR6-NEXT: .cfi_offset 16, -12
540-
; MMR6-NEXT: addu $16, $2, $25
534+
; MMR6-NEXT: addu $gp, $2, $25
541535
; MMR6-NEXT: move $1, $7
542-
; MMR6-NEXT: lw $7, 68($sp)
543-
; MMR6-NEXT: lw $17, 72($sp)
544-
; MMR6-NEXT: lw $3, 76($sp)
536+
; MMR6-NEXT: lw $7, 60($sp)
537+
; MMR6-NEXT: lw $17, 64($sp)
538+
; MMR6-NEXT: lw $3, 68($sp)
545539
; MMR6-NEXT: move $2, $sp
546540
; MMR6-NEXT: sw16 $3, 28($2)
547541
; MMR6-NEXT: sw16 $17, 24($2)
548542
; MMR6-NEXT: sw16 $7, 20($2)
549-
; MMR6-NEXT: lw $3, 64($sp)
543+
; MMR6-NEXT: lw $3, 56($sp)
550544
; MMR6-NEXT: sw16 $3, 16($2)
551-
; MMR6-NEXT: lw $25, %call16(__modti3)($16)
545+
; MMR6-NEXT: lw $25, %call16(__modti3)($gp)
552546
; MMR6-NEXT: move $7, $1
553-
; MMR6-NEXT: move $gp, $16
554547
; MMR6-NEXT: jalr $25
555-
; MMR6-NEXT: lw $16, 36($sp) # 4-byte Folded Reload
556-
; MMR6-NEXT: lw $17, 40($sp) # 4-byte Folded Reload
557-
; MMR6-NEXT: lw $ra, 44($sp) # 4-byte Folded Reload
558-
; MMR6-NEXT: addiu $sp, $sp, 48
548+
; MMR6-NEXT: lw $17, 32($sp) # 4-byte Folded Reload
549+
; MMR6-NEXT: lw $ra, 36($sp) # 4-byte Folded Reload
550+
; MMR6-NEXT: addiu $sp, $sp, 40
559551
; MMR6-NEXT: jrc $ra
560552
entry:
561553
%r = srem i128 %a, %b

0 commit comments

Comments
 (0)