@@ -232,24 +232,23 @@ bool AArch64TargetInfo::validateTarget(DiagnosticsEngine &Diags) const {
232232
233233bool AArch64TargetInfo::validateGlobalRegisterVariable (
234234 StringRef RegName, unsigned RegSize, bool &HasSizeMismatch) const {
235- if (RegName.starts_with (" w" )) {
236- HasSizeMismatch = RegSize != 32 ;
237- return true ;
238- }
239235 if (RegName == " sp" ) {
240236 HasSizeMismatch = RegSize != 64 ;
241237 return true ;
242238 }
243- if (RegName.starts_with (" x" )) {
239+ if (RegName.starts_with (" w" ))
240+ HasSizeMismatch = RegSize != 32 ;
241+ else if (RegName.starts_with (" x" ))
244242 HasSizeMismatch = RegSize != 64 ;
245- // Check if the register is reserved. See also
246- // AArch64TargetLowering::getRegisterByName().
247- return RegName == " x0" ||
248- (RegName == " x18" &&
249- llvm::AArch64::isX18ReservedByDefault (getTriple ())) ||
250- getTargetOpts ().FeatureMap .lookup ((" reserve-" + RegName).str ());
251- }
252- return false ;
243+ else
244+ return false ;
245+ StringRef RegNum = RegName.drop_front ();
246+ // Check if the register is reserved. See also
247+ // AArch64TargetLowering::getRegisterByName().
248+ return RegNum == " 0" ||
249+ (RegNum == " 18" &&
250+ llvm::AArch64::isX18ReservedByDefault (getTriple ())) ||
251+ getTargetOpts ().FeatureMap .lookup ((" reserve-x" + RegNum).str ());
253252}
254253
255254bool AArch64TargetInfo::validateBranchProtection (StringRef Spec, StringRef,
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