Don't copy over TSFlags

Author: lukel97

llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td

@@ -550,10 +550,6 @@ class RISCVVPseudo<dag outs, dag ins, list<dag> pattern, string opcodestr = "",
   // SEW = 0 is used to denote that the Pseudo is not SEW specific (or unknown).
   bits<8> SEW = 0;
   bit IncludeInInversePseudoTable = 1;
-
-  // Set common TSFlags in RVInst from the base instruction.
-  let ElementsDependOn = !cast<RVInst>(BaseInstr).ElementsDependOn;
-  let DestEEW = !cast<RVInst>(BaseInstr).DestEEW;
 }
 
 // The actual table.

llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp

@@ -33,6 +33,7 @@ namespace {
 class RISCVVLOptimizer : public MachineFunctionPass {
   const MachineRegisterInfo *MRI;
   const MachineDominatorTree *MDT;
+  const TargetInstrInfo *TII;
 
 public:
   static char ID;
@@ -1291,7 +1292,8 @@ bool RISCVVLOptimizer::isCandidate(const MachineInstr &MI) const {
     return false;
   }
 
-  assert(!RISCVII::elementsDependOnVL(MI.getDesc().TSFlags) &&
+  assert(!RISCVII::elementsDependOnVL(
+             TII->get(RISCV::getRVVMCOpcode(MI.getOpcode())).TSFlags) &&
          "Instruction shouldn't be supported if elements depend on VL");
 
   assert(MI.getOperand(0).isReg() &&
@@ -1495,6 +1497,8 @@ bool RISCVVLOptimizer::runOnMachineFunction(MachineFunction &MF) {
   if (!ST.hasVInstructions())
     return false;
 
+  TII = ST.getInstrInfo();
+
   // For each instruction that defines a vector, compute what VL its
   // downstream users demand.
   for (MachineBasicBlock *MBB : post_order(&MF)) {

llvm/lib/Target/RISCV/RISCVVectorPeephole.cpp

@@ -91,7 +91,8 @@ bool RISCVVectorPeephole::hasSameEEW(const MachineInstr &User,
       User.getOperand(RISCVII::getSEWOpNum(User.getDesc())).getImm();
   unsigned SrcLog2SEW =
       Src.getOperand(RISCVII::getSEWOpNum(Src.getDesc())).getImm();
-  unsigned SrcLog2EEW = RISCV::getDestLog2EEW(Src.getDesc(), SrcLog2SEW);
+  unsigned SrcLog2EEW = RISCV::getDestLog2EEW(
+      TII->get(RISCV::getRVVMCOpcode(Src.getOpcode())), SrcLog2SEW);
   return SrcLog2EEW == UserLog2SEW;
 }
 
@@ -169,8 +170,8 @@ bool RISCVVectorPeephole::tryToReduceVL(MachineInstr &MI) const {
     if (!hasSameEEW(MI, *Src))
       continue;
 
-    bool ElementsDependOnVL =
-        RISCVII::elementsDependOnVL(Src->getDesc().TSFlags);
+    bool ElementsDependOnVL = RISCVII::elementsDependOnVL(
+        TII->get(RISCV::getRVVMCOpcode(Src->getOpcode())).TSFlags);
     if (ElementsDependOnVL || Src->mayRaiseFPException())
       continue;
 
@@ -759,11 +760,11 @@ bool RISCVVectorPeephole::foldVMergeToMask(MachineInstr &MI) const {
   else
     return false;
 
-  if (RISCVII::elementsDependOnVL(True.getDesc().TSFlags) &&
-      !TrueVL.isIdenticalTo(MinVL))
+  unsigned RVVTSFlags =
+      TII->get(RISCV::getRVVMCOpcode(True.getOpcode())).TSFlags;
+  if (RISCVII::elementsDependOnVL(RVVTSFlags) && !TrueVL.isIdenticalTo(MinVL))
     return false;
-  if (RISCVII::elementsDependOnMask(True.getDesc().TSFlags) &&
-      !isAllOnesMask(Mask))
+  if (RISCVII::elementsDependOnMask(RVVTSFlags) && !isAllOnesMask(Mask))
     return false;
 
   // Use a tumu policy, relaxing it to tail agnostic provided that the passthru