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‎llvm/docs/QualGroup.rst‎

Lines changed: 23 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1,3 +1,8 @@
1+
.. CHANGE TRACKER for reference
2+
.. Purpose: Fixed document location and added Current Topics & Backlog
3+
.. Author: Carlos Andres Ramirez
4+
.. Last updated: 2025-09-08 by Carlos Ramirez
5+
16
========================
27
LLVM Qualification Group
38
========================
@@ -48,6 +53,20 @@ Participation is open to anyone interested. There are several ways to get involv
4853

4954
We welcome contributors from diverse backgrounds, organizations, and experience levels.
5055

56+
Current Topics & Backlog
57+
========================
58+
59+
Our working group is actively engaged in discussions about the project's
60+
direction and tackling technical challenges. You can find our current
61+
discussions, challenges, and the project backlog in the following
62+
document.
63+
64+
`Backlog document <https://docs.google.com/document/d/10YZZ72ba09Ck_OiJaP9C4-7DeUiveaIKTE3IkaSKjzA/edit?usp=sharing>`
65+
66+
This document serves as our central hub for all ongoing topics and will
67+
be updated regularly to reflect our progress. We welcome your
68+
contributions and feedback.
69+
5170
Meeting Materials
5271
=================
5372

@@ -60,9 +79,10 @@ on the LLVM Discourse forum: `Meeting Agendas and Minutes <https://discourse.llv
6079
Slides used to support discussions during sync-up meetings are stored in LLVM's GitHub repository.
6180

6281
Available slides:
63-
* `September 2025 <../qual-wg/slides/202509_llvm_qual_wg.pdf>`_
64-
* `August 2025 <../qual-wg/slides/202508_llvm_qual_wg.pdf>`_
65-
* `July 2025 <../qual-wg/slides/202507_llvm_qual_wg.pdf>`_
82+
83+
* `September 2025 <qual-wg/slides/202509_llvm_qual_wg.pdf>`_
84+
* `August 2025 <qual-wg/slides/202508_llvm_qual_wg.pdf>`_
85+
* `July 2025 <qual-wg/slides/202507_llvm_qual_wg.pdf>`_
6686
* (add future entries here)
6787

6888
A future patch will migrate these slide files to the `llvm-www` repository, once

‎llvm/lib/CodeGen/MachineInstrBundle.cpp‎

Lines changed: 7 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -133,7 +133,6 @@ void llvm::finalizeBundle(MachineBasicBlock &MBB,
133133
SmallSetVector<Register, 32> LocalDefs;
134134
BitVector LocalDefsP(TRI->getNumRegUnits());
135135
SmallSet<Register, 8> DeadDefSet;
136-
SmallSet<Register, 16> KilledDefSet;
137136
SmallSetVector<Register, 8> ExternUses;
138137
SmallSet<Register, 8> KilledUseSet;
139138
SmallSet<Register, 8> UndefUseSet;
@@ -151,7 +150,7 @@ void llvm::finalizeBundle(MachineBasicBlock &MBB,
151150
MO.setIsInternalRead();
152151
if (MO.isKill()) {
153152
// Internal def is now killed.
154-
KilledDefSet.insert(Reg);
153+
DeadDefSet.insert(Reg);
155154
}
156155
} else {
157156
if (ExternUses.insert(Reg)) {
@@ -171,19 +170,18 @@ void llvm::finalizeBundle(MachineBasicBlock &MBB,
171170
continue;
172171

173172
if (LocalDefs.insert(Reg)) {
174-
if (MO.isDead())
175-
DeadDefSet.insert(Reg);
176-
else if (Reg.isPhysical())
173+
if (!MO.isDead() && Reg.isPhysical()) {
177174
for (MCRegUnit Unit : TRI->regunits(Reg.asMCReg()))
178175
LocalDefsP.set(Unit);
176+
}
179177
} else {
180-
// Re-defined inside the bundle, it's no longer killed.
181-
KilledDefSet.erase(Reg);
182178
if (!MO.isDead()) {
183-
// Previously defined but dead.
179+
// Re-defined inside the bundle, it's no longer dead.
184180
DeadDefSet.erase(Reg);
185181
}
186182
}
183+
if (MO.isDead())
184+
DeadDefSet.insert(Reg);
187185
}
188186

189187
// Set FrameSetup/FrameDestroy for the bundle. If any of the instructions
@@ -196,7 +194,7 @@ void llvm::finalizeBundle(MachineBasicBlock &MBB,
196194

197195
for (Register Reg : LocalDefs) {
198196
// If it's not live beyond end of the bundle, mark it dead.
199-
bool isDead = DeadDefSet.contains(Reg) || KilledDefSet.contains(Reg);
197+
bool isDead = DeadDefSet.contains(Reg);
200198
MIB.addReg(Reg, getDefRegState(true) | getDeadRegState(isDead) |
201199
getImplRegState(true));
202200
}

‎llvm/lib/Target/Mips/MipsSubtarget.cpp‎

Lines changed: 2 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -245,20 +245,10 @@ CodeGenOptLevel MipsSubtarget::getOptLevelToEnablePostRAScheduler() const {
245245
MipsSubtarget &
246246
MipsSubtarget::initializeSubtargetDependencies(StringRef CPU, StringRef FS,
247247
const TargetMachine &TM) {
248-
const Triple &TT = TM.getTargetTriple();
249-
StringRef CPUName = MIPS_MC::selectMipsCPU(TT, CPU);
250-
251-
std::string FullFS;
252-
if (getABI().ArePtrs64bit()) {
253-
FullFS = "+ptr64";
254-
if (!FS.empty())
255-
FullFS = (Twine(FullFS) + "," + FS).str();
256-
} else {
257-
FullFS = FS.str();
258-
}
248+
StringRef CPUName = MIPS_MC::selectMipsCPU(TM.getTargetTriple(), CPU);
259249

260250
// Parse features string.
261-
ParseSubtargetFeatures(CPUName, /*TuneCPU=*/CPUName, FullFS);
251+
ParseSubtargetFeatures(CPUName, /*TuneCPU*/ CPUName, FS);
262252
// Initialize scheduling itinerary for the specified CPU.
263253
InstrItins = getInstrItineraryForCPU(CPUName);
264254

‎llvm/test/CodeGen/AArch64/blr-bti-preserves-operands.mir‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -8,7 +8,7 @@
88
# The arguments to the call must become implicit arguments, because the branch
99
# only expects to get 1 explicit operand which is the branch target.
1010

11-
# CHECK: BUNDLE implicit-def $lr, implicit-def $sp, implicit $sp, implicit $x0, implicit $w1 {
11+
# CHECK: BUNDLE implicit-def dead $lr, implicit-def $sp, implicit $sp, implicit $x0, implicit $w1 {
1212
# CHECK: BL @_setjmp, csr_aarch64_aapcs, implicit-def $lr, implicit $sp, implicit $x0, implicit $w1, implicit-def dead $lr, implicit $sp, implicit-def $sp
1313
# CHECK: HINT 36
1414
# CHECK: }

‎llvm/test/CodeGen/AMDGPU/finalizebundle.mir‎

Lines changed: 18 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -16,3 +16,21 @@ body: |
1616
$vgpr2_vgpr3 = V_LSHLREV_B64_pseudo_e32 1, $vgpr0_vgpr1, implicit $exec
1717
$vgpr3_vgpr4 = V_LSHLREV_B64_pseudo_e32 1, $vgpr1_vgpr2, implicit $exec
1818
...
19+
20+
---
21+
name: test_dead_redef
22+
body: |
23+
bb.0:
24+
liveins: $vgpr0
25+
; CHECK-LABEL: name: test_dead_redef
26+
; CHECK: liveins: $vgpr0
27+
; CHECK-NEXT: {{ $}}
28+
; CHECK-NEXT: BUNDLE implicit-def dead $vgpr1, implicit-def $vgpr0, implicit $vgpr0, implicit $exec {
29+
; CHECK-NEXT: $vgpr1 = V_MOV_B32_e32 $vgpr0, implicit $exec
30+
; CHECK-NEXT: $vgpr0 = V_MOV_B32_e32 internal $vgpr1, implicit $exec
31+
; CHECK-NEXT: dead $vgpr1 = V_MOV_B32_e32 internal $vgpr0, implicit $exec
32+
; CHECK-NEXT: }
33+
$vgpr1 = V_MOV_B32_e32 $vgpr0, implicit $exec
34+
$vgpr0 = V_MOV_B32_e32 $vgpr1, implicit $exec
35+
dead $vgpr1 = V_MOV_B32_e32 $vgpr0, implicit $exec
36+
...

‎llvm/test/Transforms/LoopVectorize/AArch64/sve-epilog-vscale-fixed.ll‎

Lines changed: 28 additions & 24 deletions
Original file line numberDiff line numberDiff line change
@@ -24,20 +24,21 @@ target triple = "aarch64-linux-gnu"
2424
; DEBUG-EPILOG-PREFER-SCALABLE: Create Skeleton for epilogue vectorized loop (first pass)
2525
; DEBUG-EPILOG-PREFER-SCALABLE: Main Loop VF:vscale x 16, Main Loop UF:2, Epilogue Loop VF:vscale x 8, Epilogue Loop UF:1
2626

27-
define void @main_vf_vscale_x_16(ptr %A) #0 {
27+
define void @main_vf_vscale_x_16(ptr %A, i64 %n) #0 {
2828
; CHECK-LABEL: @main_vf_vscale_x_16(
2929
; CHECK-NEXT: iter.check:
30-
; CHECK-NEXT: br i1 false, label [[VEC_EPILOG_SCALAR_PH:%.*]], label [[VECTOR_MAIN_LOOP_ITER_CHECK:%.*]]
30+
; CHECK-NEXT: [[MIN_ITERS_CHECK1:%.*]] = icmp ult i64 [[N:%.*]], 8
31+
; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK1]], label [[VEC_EPILOG_SCALAR_PH:%.*]], label [[VECTOR_MAIN_LOOP_ITER_CHECK:%.*]]
3132
; CHECK: vector.main.loop.iter.check:
3233
; CHECK-NEXT: [[TMP0:%.*]] = call i64 @llvm.vscale.i64()
3334
; CHECK-NEXT: [[TMP1:%.*]] = shl nuw i64 [[TMP0]], 5
34-
; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 1024, [[TMP1]]
35+
; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[N]], [[TMP1]]
3536
; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label [[VEC_EPILOG_PH:%.*]], label [[VECTOR_PH:%.*]]
3637
; CHECK: vector.ph:
3738
; CHECK-NEXT: [[TMP2:%.*]] = call i64 @llvm.vscale.i64()
3839
; CHECK-NEXT: [[TMP3:%.*]] = mul nuw i64 [[TMP2]], 32
39-
; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i64 1024, [[TMP3]]
40-
; CHECK-NEXT: [[N_VEC:%.*]] = sub i64 1024, [[N_MOD_VF]]
40+
; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[N]], [[TMP3]]
41+
; CHECK-NEXT: [[N_VEC:%.*]] = sub i64 [[N]], [[N_MOD_VF]]
4142
; CHECK-NEXT: br label [[VECTOR_BODY:%.*]]
4243
; CHECK: vector.body:
4344
; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]
@@ -51,45 +52,48 @@ define void @main_vf_vscale_x_16(ptr %A) #0 {
5152
; CHECK-NEXT: [[TMP8:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
5253
; CHECK-NEXT: br i1 [[TMP8]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
5354
; CHECK: middle.block:
54-
; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i64 1024, [[N_VEC]]
55+
; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[N]], [[N_VEC]]
5556
; CHECK-NEXT: br i1 [[CMP_N]], label [[EXIT:%.*]], label [[VEC_EPILOG_ITER_CHECK:%.*]]
5657
; CHECK: vec.epilog.iter.check:
57-
; CHECK-NEXT: [[N_VEC_REMAINING:%.*]] = sub i64 1024, [[N_VEC]]
58+
; CHECK-NEXT: [[N_VEC_REMAINING:%.*]] = sub i64 [[N]], [[N_VEC]]
5859
; CHECK-NEXT: [[MIN_EPILOG_ITERS_CHECK:%.*]] = icmp ult i64 [[N_VEC_REMAINING]], 8
59-
; CHECK-NEXT: br i1 [[MIN_EPILOG_ITERS_CHECK]], label [[VEC_EPILOG_SCALAR_PH]], label [[VEC_EPILOG_PH]]
60+
; CHECK-NEXT: br i1 [[MIN_EPILOG_ITERS_CHECK]], label [[VEC_EPILOG_SCALAR_PH]], label [[VEC_EPILOG_PH]], !prof [[PROF3:![0-9]+]]
6061
; CHECK: vec.epilog.ph:
6162
; CHECK-NEXT: [[VEC_EPILOG_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], [[VEC_EPILOG_ITER_CHECK]] ], [ 0, [[VECTOR_MAIN_LOOP_ITER_CHECK]] ]
63+
; CHECK-NEXT: [[N_MOD_VF2:%.*]] = urem i64 [[N]], 8
64+
; CHECK-NEXT: [[N_VEC3:%.*]] = sub i64 [[N]], [[N_MOD_VF2]]
6265
; CHECK-NEXT: br label [[VEC_EPILOG_VECTOR_BODY:%.*]]
6366
; CHECK: vec.epilog.vector.body:
6467
; CHECK-NEXT: [[INDEX1:%.*]] = phi i64 [ [[VEC_EPILOG_RESUME_VAL]], [[VEC_EPILOG_PH]] ], [ [[INDEX_NEXT2:%.*]], [[VEC_EPILOG_VECTOR_BODY]] ]
6568
; CHECK-NEXT: [[TMP9:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 [[INDEX1]]
6669
; CHECK-NEXT: store <8 x i8> splat (i8 1), ptr [[TMP9]], align 1
6770
; CHECK-NEXT: [[INDEX_NEXT2]] = add nuw i64 [[INDEX1]], 8
68-
; CHECK-NEXT: [[TMP10:%.*]] = icmp eq i64 [[INDEX_NEXT2]], 1024
69-
; CHECK-NEXT: br i1 [[TMP10]], label [[VEC_EPILOG_MIDDLE_BLOCK:%.*]], label [[VEC_EPILOG_VECTOR_BODY]], !llvm.loop [[LOOP3:![0-9]+]]
71+
; CHECK-NEXT: [[TMP10:%.*]] = icmp eq i64 [[INDEX_NEXT2]], [[N_VEC3]]
72+
; CHECK-NEXT: br i1 [[TMP10]], label [[VEC_EPILOG_MIDDLE_BLOCK:%.*]], label [[VEC_EPILOG_VECTOR_BODY]], !llvm.loop [[LOOP4:![0-9]+]]
7073
; CHECK: vec.epilog.middle.block:
71-
; CHECK-NEXT: br i1 true, label [[EXIT]], label [[VEC_EPILOG_SCALAR_PH]]
74+
; CHECK-NEXT: [[CMP_N6:%.*]] = icmp eq i64 [[N]], [[N_VEC3]]
75+
; CHECK-NEXT: br i1 [[CMP_N6]], label [[EXIT]], label [[VEC_EPILOG_SCALAR_PH]]
7276
; CHECK: vec.epilog.scalar.ph:
73-
; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ 1024, [[VEC_EPILOG_MIDDLE_BLOCK]] ], [ [[N_VEC]], [[VEC_EPILOG_ITER_CHECK]] ], [ 0, [[ITER_CHECK:%.*]] ]
77+
; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC3]], [[VEC_EPILOG_MIDDLE_BLOCK]] ], [ [[N_VEC]], [[VEC_EPILOG_ITER_CHECK]] ], [ 0, [[ITER_CHECK:%.*]] ]
7478
; CHECK-NEXT: br label [[FOR_BODY:%.*]]
7579
; CHECK: for.body:
7680
;
7781
; CHECK-EPILOG-PREFER-SCALABLE-LABEL: @main_vf_vscale_x_16(
7882
; CHECK-EPILOG-PREFER-SCALABLE-NEXT: iter.check:
7983
; CHECK-EPILOG-PREFER-SCALABLE-NEXT: [[TMP0:%.*]] = call i64 @llvm.vscale.i64()
8084
; CHECK-EPILOG-PREFER-SCALABLE-NEXT: [[TMP1:%.*]] = shl nuw i64 [[TMP0]], 3
81-
; CHECK-EPILOG-PREFER-SCALABLE-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 1024, [[TMP1]]
85+
; CHECK-EPILOG-PREFER-SCALABLE-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[N:%.*]], [[TMP1]]
8286
; CHECK-EPILOG-PREFER-SCALABLE-NEXT: br i1 [[MIN_ITERS_CHECK]], label [[VEC_EPILOG_SCALAR_PH:%.*]], label [[VECTOR_MAIN_LOOP_ITER_CHECK:%.*]]
8387
; CHECK-EPILOG-PREFER-SCALABLE: vector.main.loop.iter.check:
8488
; CHECK-EPILOG-PREFER-SCALABLE-NEXT: [[TMP2:%.*]] = call i64 @llvm.vscale.i64()
8589
; CHECK-EPILOG-PREFER-SCALABLE-NEXT: [[TMP3:%.*]] = shl nuw i64 [[TMP2]], 5
86-
; CHECK-EPILOG-PREFER-SCALABLE-NEXT: [[MIN_ITERS_CHECK1:%.*]] = icmp ult i64 1024, [[TMP3]]
90+
; CHECK-EPILOG-PREFER-SCALABLE-NEXT: [[MIN_ITERS_CHECK1:%.*]] = icmp ult i64 [[N]], [[TMP3]]
8791
; CHECK-EPILOG-PREFER-SCALABLE-NEXT: br i1 [[MIN_ITERS_CHECK1]], label [[VEC_EPILOG_PH:%.*]], label [[VECTOR_PH:%.*]]
8892
; CHECK-EPILOG-PREFER-SCALABLE: vector.ph:
8993
; CHECK-EPILOG-PREFER-SCALABLE-NEXT: [[TMP4:%.*]] = call i64 @llvm.vscale.i64()
9094
; CHECK-EPILOG-PREFER-SCALABLE-NEXT: [[TMP5:%.*]] = mul nuw i64 [[TMP4]], 32
91-
; CHECK-EPILOG-PREFER-SCALABLE-NEXT: [[N_MOD_VF:%.*]] = urem i64 1024, [[TMP5]]
92-
; CHECK-EPILOG-PREFER-SCALABLE-NEXT: [[N_VEC:%.*]] = sub i64 1024, [[N_MOD_VF]]
95+
; CHECK-EPILOG-PREFER-SCALABLE-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[N]], [[TMP5]]
96+
; CHECK-EPILOG-PREFER-SCALABLE-NEXT: [[N_VEC:%.*]] = sub i64 [[N]], [[N_MOD_VF]]
9397
; CHECK-EPILOG-PREFER-SCALABLE-NEXT: br label [[VECTOR_BODY:%.*]]
9498
; CHECK-EPILOG-PREFER-SCALABLE: vector.body:
9599
; CHECK-EPILOG-PREFER-SCALABLE-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]
@@ -103,30 +107,30 @@ define void @main_vf_vscale_x_16(ptr %A) #0 {
103107
; CHECK-EPILOG-PREFER-SCALABLE-NEXT: [[TMP10:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
104108
; CHECK-EPILOG-PREFER-SCALABLE-NEXT: br i1 [[TMP10]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
105109
; CHECK-EPILOG-PREFER-SCALABLE: middle.block:
106-
; CHECK-EPILOG-PREFER-SCALABLE-NEXT: [[CMP_N:%.*]] = icmp eq i64 1024, [[N_VEC]]
110+
; CHECK-EPILOG-PREFER-SCALABLE-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[N]], [[N_VEC]]
107111
; CHECK-EPILOG-PREFER-SCALABLE-NEXT: br i1 [[CMP_N]], label [[EXIT:%.*]], label [[VEC_EPILOG_ITER_CHECK:%.*]]
108112
; CHECK-EPILOG-PREFER-SCALABLE: vec.epilog.iter.check:
109-
; CHECK-EPILOG-PREFER-SCALABLE-NEXT: [[N_VEC_REMAINING:%.*]] = sub i64 1024, [[N_VEC]]
113+
; CHECK-EPILOG-PREFER-SCALABLE-NEXT: [[N_VEC_REMAINING:%.*]] = sub i64 [[N]], [[N_VEC]]
110114
; CHECK-EPILOG-PREFER-SCALABLE-NEXT: [[TMP11:%.*]] = call i64 @llvm.vscale.i64()
111115
; CHECK-EPILOG-PREFER-SCALABLE-NEXT: [[TMP12:%.*]] = shl nuw i64 [[TMP11]], 3
112116
; CHECK-EPILOG-PREFER-SCALABLE-NEXT: [[MIN_EPILOG_ITERS_CHECK:%.*]] = icmp ult i64 [[N_VEC_REMAINING]], [[TMP12]]
113-
; CHECK-EPILOG-PREFER-SCALABLE-NEXT: br i1 [[MIN_EPILOG_ITERS_CHECK]], label [[VEC_EPILOG_SCALAR_PH]], label [[VEC_EPILOG_PH]]
117+
; CHECK-EPILOG-PREFER-SCALABLE-NEXT: br i1 [[MIN_EPILOG_ITERS_CHECK]], label [[VEC_EPILOG_SCALAR_PH]], label [[VEC_EPILOG_PH]], !prof [[PROF3:![0-9]+]]
114118
; CHECK-EPILOG-PREFER-SCALABLE: vec.epilog.ph:
115119
; CHECK-EPILOG-PREFER-SCALABLE-NEXT: [[VEC_EPILOG_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], [[VEC_EPILOG_ITER_CHECK]] ], [ 0, [[VECTOR_MAIN_LOOP_ITER_CHECK]] ]
116120
; CHECK-EPILOG-PREFER-SCALABLE-NEXT: [[TMP13:%.*]] = call i64 @llvm.vscale.i64()
117121
; CHECK-EPILOG-PREFER-SCALABLE-NEXT: [[TMP14:%.*]] = mul nuw i64 [[TMP13]], 8
118-
; CHECK-EPILOG-PREFER-SCALABLE-NEXT: [[N_MOD_VF2:%.*]] = urem i64 1024, [[TMP14]]
119-
; CHECK-EPILOG-PREFER-SCALABLE-NEXT: [[N_VEC3:%.*]] = sub i64 1024, [[N_MOD_VF2]]
122+
; CHECK-EPILOG-PREFER-SCALABLE-NEXT: [[N_MOD_VF2:%.*]] = urem i64 [[N]], [[TMP14]]
123+
; CHECK-EPILOG-PREFER-SCALABLE-NEXT: [[N_VEC3:%.*]] = sub i64 [[N]], [[N_MOD_VF2]]
120124
; CHECK-EPILOG-PREFER-SCALABLE-NEXT: br label [[VEC_EPILOG_VECTOR_BODY:%.*]]
121125
; CHECK-EPILOG-PREFER-SCALABLE: vec.epilog.vector.body:
122126
; CHECK-EPILOG-PREFER-SCALABLE-NEXT: [[INDEX4:%.*]] = phi i64 [ [[VEC_EPILOG_RESUME_VAL]], [[VEC_EPILOG_PH]] ], [ [[INDEX_NEXT5:%.*]], [[VEC_EPILOG_VECTOR_BODY]] ]
123127
; CHECK-EPILOG-PREFER-SCALABLE-NEXT: [[TMP15:%.*]] = getelementptr inbounds i8, ptr [[A]], i64 [[INDEX4]]
124128
; CHECK-EPILOG-PREFER-SCALABLE-NEXT: store <vscale x 8 x i8> splat (i8 1), ptr [[TMP15]], align 1
125129
; CHECK-EPILOG-PREFER-SCALABLE-NEXT: [[INDEX_NEXT5]] = add nuw i64 [[INDEX4]], [[TMP14]]
126130
; CHECK-EPILOG-PREFER-SCALABLE-NEXT: [[TMP16:%.*]] = icmp eq i64 [[INDEX_NEXT5]], [[N_VEC3]]
127-
; CHECK-EPILOG-PREFER-SCALABLE-NEXT: br i1 [[TMP16]], label [[VEC_EPILOG_MIDDLE_BLOCK:%.*]], label [[VEC_EPILOG_VECTOR_BODY]], !llvm.loop [[LOOP3:![0-9]+]]
131+
; CHECK-EPILOG-PREFER-SCALABLE-NEXT: br i1 [[TMP16]], label [[VEC_EPILOG_MIDDLE_BLOCK:%.*]], label [[VEC_EPILOG_VECTOR_BODY]], !llvm.loop [[LOOP4:![0-9]+]]
128132
; CHECK-EPILOG-PREFER-SCALABLE: vec.epilog.middle.block:
129-
; CHECK-EPILOG-PREFER-SCALABLE-NEXT: [[CMP_N6:%.*]] = icmp eq i64 1024, [[N_VEC3]]
133+
; CHECK-EPILOG-PREFER-SCALABLE-NEXT: [[CMP_N6:%.*]] = icmp eq i64 [[N]], [[N_VEC3]]
130134
; CHECK-EPILOG-PREFER-SCALABLE-NEXT: br i1 [[CMP_N6]], label [[EXIT]], label [[VEC_EPILOG_SCALAR_PH]]
131135
; CHECK-EPILOG-PREFER-SCALABLE: vec.epilog.scalar.ph:
132136
; CHECK-EPILOG-PREFER-SCALABLE-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC3]], [[VEC_EPILOG_MIDDLE_BLOCK]] ], [ [[N_VEC]], [[VEC_EPILOG_ITER_CHECK]] ], [ 0, [[ITER_CHECK:%.*]] ]
@@ -141,7 +145,7 @@ for.body:
141145
%arrayidx = getelementptr inbounds i8, ptr %A, i64 %iv
142146
store i8 1, ptr %arrayidx, align 1
143147
%iv.next = add nuw nsw i64 %iv, 1
144-
%exitcond = icmp ne i64 %iv.next, 1024
148+
%exitcond = icmp ne i64 %iv.next, %n
145149
br i1 %exitcond, label %for.body, label %exit
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exit:

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