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 | 1 | +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5  | 
 | 2 | +; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1200 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX12-SDAG %s  | 
 | 3 | +; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1200 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX12-GISEL %s  | 
 | 4 | + | 
 | 5 | +define i1 @func1() {  | 
 | 6 | +; GFX12-SDAG-LABEL: func1:  | 
 | 7 | +; GFX12-SDAG:       ; %bb.0:  | 
 | 8 | +; GFX12-SDAG-NEXT:    s_wait_loadcnt_dscnt 0x0  | 
 | 9 | +; GFX12-SDAG-NEXT:    s_wait_expcnt 0x0  | 
 | 10 | +; GFX12-SDAG-NEXT:    s_wait_samplecnt 0x0  | 
 | 11 | +; GFX12-SDAG-NEXT:    s_wait_bvhcnt 0x0  | 
 | 12 | +; GFX12-SDAG-NEXT:    s_wait_kmcnt 0x0  | 
 | 13 | +; GFX12-SDAG-NEXT:    s_wait_storecnt 0x0  | 
 | 14 | +; GFX12-SDAG-NEXT:    s_barrier_signal_isfirst -1  | 
 | 15 | +; GFX12-SDAG-NEXT:    s_cselect_b32 s0, -1, 0  | 
 | 16 | +; GFX12-SDAG-NEXT:    s_wait_alu 0xfffe  | 
 | 17 | +; GFX12-SDAG-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s0  | 
 | 18 | +; GFX12-SDAG-NEXT:    s_wait_kmcnt 0x0  | 
 | 19 | +; GFX12-SDAG-NEXT:    s_setpc_b64 s[30:31]  | 
 | 20 | +;  | 
 | 21 | +; GFX12-GISEL-LABEL: func1:  | 
 | 22 | +; GFX12-GISEL:       ; %bb.0:  | 
 | 23 | +; GFX12-GISEL-NEXT:    s_wait_loadcnt_dscnt 0x0  | 
 | 24 | +; GFX12-GISEL-NEXT:    s_wait_expcnt 0x0  | 
 | 25 | +; GFX12-GISEL-NEXT:    s_wait_samplecnt 0x0  | 
 | 26 | +; GFX12-GISEL-NEXT:    s_wait_bvhcnt 0x0  | 
 | 27 | +; GFX12-GISEL-NEXT:    s_wait_kmcnt 0x0  | 
 | 28 | +; GFX12-GISEL-NEXT:    s_wait_storecnt 0x0  | 
 | 29 | +; GFX12-GISEL-NEXT:    s_barrier_signal_isfirst -1  | 
 | 30 | +; GFX12-GISEL-NEXT:    s_cselect_b32 s0, 1, 0  | 
 | 31 | +; GFX12-GISEL-NEXT:    s_wait_alu 0xfffe  | 
 | 32 | +; GFX12-GISEL-NEXT:    v_mov_b32_e32 v0, s0  | 
 | 33 | +; GFX12-GISEL-NEXT:    s_wait_kmcnt 0x0  | 
 | 34 | +; GFX12-GISEL-NEXT:    s_setpc_b64 s[30:31]  | 
 | 35 | +    %r = call i1 @llvm.amdgcn.s.barrier.signal.isfirst(i32 -1)  | 
 | 36 | +    ret i1 %r  | 
 | 37 | +}  | 
 | 38 | + | 
 | 39 | +declare i1 @llvm.amdgcn.s.barrier.signal.isfirst(i32)  | 
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