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AMDGPU: Precommit a lit test
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
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; RUN: llc -global-isel=0 -mtriple=amdgcn -mcpu=gfx1200 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX12-SDAG %s
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; RUN: llc -global-isel=1 -mtriple=amdgcn -mcpu=gfx1200 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX12-GISEL %s
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define i1 @func1() {
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; GFX12-SDAG-LABEL: func1:
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; GFX12-SDAG: ; %bb.0:
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; GFX12-SDAG-NEXT: s_wait_loadcnt_dscnt 0x0
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; GFX12-SDAG-NEXT: s_wait_expcnt 0x0
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; GFX12-SDAG-NEXT: s_wait_samplecnt 0x0
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; GFX12-SDAG-NEXT: s_wait_bvhcnt 0x0
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; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
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; GFX12-SDAG-NEXT: s_wait_storecnt 0x0
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; GFX12-SDAG-NEXT: s_barrier_signal_isfirst -1
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; GFX12-SDAG-NEXT: s_cselect_b32 s0, -1, 0
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; GFX12-SDAG-NEXT: s_wait_alu 0xfffe
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; GFX12-SDAG-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
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; GFX12-SDAG-NEXT: s_wait_kmcnt 0x0
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; GFX12-SDAG-NEXT: s_setpc_b64 s[30:31]
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;
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; GFX12-GISEL-LABEL: func1:
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; GFX12-GISEL: ; %bb.0:
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; GFX12-GISEL-NEXT: s_wait_loadcnt_dscnt 0x0
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; GFX12-GISEL-NEXT: s_wait_expcnt 0x0
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; GFX12-GISEL-NEXT: s_wait_samplecnt 0x0
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; GFX12-GISEL-NEXT: s_wait_bvhcnt 0x0
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; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
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; GFX12-GISEL-NEXT: s_wait_storecnt 0x0
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; GFX12-GISEL-NEXT: s_barrier_signal_isfirst -1
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; GFX12-GISEL-NEXT: s_cselect_b32 s0, 1, 0
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; GFX12-GISEL-NEXT: s_wait_alu 0xfffe
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; GFX12-GISEL-NEXT: v_mov_b32_e32 v0, s0
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; GFX12-GISEL-NEXT: s_wait_kmcnt 0x0
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; GFX12-GISEL-NEXT: s_setpc_b64 s[30:31]
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%r = call i1 @llvm.amdgcn.s.barrier.signal.isfirst(i32 -1)
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ret i1 %r
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}
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declare i1 @llvm.amdgcn.s.barrier.signal.isfirst(i32)

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