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[AArch64][llvm] Reject assembler for invalid TLBIP instructions (#162090)
Some invalid assembler is currently allowed for `tlbip` sys alias instructions, since there's only a single table in tablegen for both `tlbi` and `tlbip` instructions. However, the latter is only a subset of the former, so invalid machine code is generated for `tlbip` instructions which don't actually exist. Define a `TLBI_and_TLBIP` and `TLBI_only` enum (wish tablegen had first class enum support), so that only valid `tlbip` instructions are created in the `TLBIPEntry` table, and instructions which are not valid are correctly rejected. Add new testcases for this. (See the Arm ARM DDI 0487 L.b pages C5-802 to 809 where valid `tlbi` and `tlbip` instructions are defined). For example, before this change, both of the following are accepted. Subsequent to this change, `tlbip` is correctly rejected: ``` % llvm-mc -triple=aarch64 <<< "tlbi alle1" --show-encoding tlbi alle1 // encoding: [0x9f,0x87,0x0c,0xd5] % llvm-mc -triple=aarch64 -mattr=+d128 <<< "tlbip alle1, x0, x1" <stdin>:1:7: error: invalid operand for TLBIP instruction tlbip alle1 ^ ```
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‎llvm/lib/Target/AArch64/AArch64SystemOperands.td‎

Lines changed: 121 additions & 102 deletions
Original file line numberDiff line numberDiff line change
@@ -816,8 +816,8 @@ def : BTI<"jc", 0b110>;
816816
// TLBI (translation lookaside buffer invalidate) instruction options.
817817
//===----------------------------------------------------------------------===//
818818

819-
class TLBIEntry<string name, bits<3> op1, bits<4> crn, bits<4> crm,
820-
bits<3> op2, bit needsreg> {
819+
class TLBICommon<string name, bits<3> op1, bits<4> crn, bits<4> crm,
820+
bits<3> op2, bit needsreg> {
821821
string Name = name;
822822
bits<14> Encoding;
823823
let Encoding{13-11} = op1;
@@ -830,131 +830,150 @@ class TLBIEntry<string name, bits<3> op1, bits<4> crn, bits<4> crm,
830830
code RequiresStr = [{ { }] # !interleave(Requires # ExtraRequires, [{, }]) # [{ } }];
831831
}
832832

833-
def TLBITable : GenericTable {
834-
let FilterClass = "TLBIEntry";
835-
let CppTypeName = "TLBI";
836-
let Fields = ["Name", "Encoding", "NeedsReg", "RequiresStr"];
837-
838-
let PrimaryKey = ["Encoding"];
839-
let PrimaryKeyName = "lookupTLBIByEncoding";
833+
class TLBIEntry<string name, bits<3> op1, bits<4> crn, bits<4> crm,
834+
bits<3> op2, bit needsreg>
835+
: TLBICommon<name, op1, crn, crm, op2, needsreg>;
836+
837+
class TLBIPEntry<string name, bits<3> op1, bits<4> crn, bits<4> crm,
838+
bits<3> op2, bit needsreg>
839+
: TLBICommon<name, op1, crn, crm, op2, needsreg>;
840+
841+
multiclass TLBITableBase {
842+
def NAME # Table : GenericTable {
843+
let FilterClass = NAME # "Entry";
844+
let CppTypeName = NAME;
845+
let Fields = ["Name", "Encoding", "NeedsReg", "RequiresStr"];
846+
let PrimaryKey = ["Encoding"];
847+
let PrimaryKeyName = "lookup" # NAME # "ByEncoding";
848+
}
849+
def lookup # NAME # ByName : SearchIndex {
850+
let Table = !cast<GenericTable>(NAME # "Table");
851+
let Key = ["Name"];
852+
}
840853
}
841854

842-
def lookupTLBIByName : SearchIndex {
843-
let Table = TLBITable;
844-
let Key = ["Name"];
845-
}
855+
defm TLBI : TLBITableBase;
856+
defm TLBIP : TLBITableBase;
846857

847-
multiclass TLBI<string name, bits<3> op1, bits<4> crn, bits<4> crm,
858+
multiclass TLBI<string name, bit hasTLBIP, bits<3> op1, bits<4> crn, bits<4> crm,
848859
bits<3> op2, bit needsreg = 1> {
849860
def : TLBIEntry<name, op1, crn, crm, op2, needsreg>;
850861
def : TLBIEntry<!strconcat(name, "nXS"), op1, crn, crm, op2, needsreg> {
851862
let Encoding{7} = 1;
852863
let ExtraRequires = ["AArch64::FeatureXS"];
853864
}
865+
if !eq(hasTLBIP, true) then {
866+
def : TLBIPEntry<name, op1, crn, crm, op2, needsreg>;
867+
def : TLBIPEntry<!strconcat(name, "nXS"), op1, crn, crm, op2, needsreg> {
868+
let Encoding{7} = 1;
869+
let ExtraRequires = ["AArch64::FeatureXS"];
870+
}
871+
}
854872
}
855873

856-
defm : TLBI<"IPAS2E1IS", 0b100, 0b1000, 0b0000, 0b001>;
857-
defm : TLBI<"IPAS2LE1IS", 0b100, 0b1000, 0b0000, 0b101>;
858-
defm : TLBI<"VMALLE1IS", 0b000, 0b1000, 0b0011, 0b000, 0>;
859-
defm : TLBI<"ALLE2IS", 0b100, 0b1000, 0b0011, 0b000, 0>;
860-
defm : TLBI<"ALLE3IS", 0b110, 0b1000, 0b0011, 0b000, 0>;
861-
defm : TLBI<"VAE1IS", 0b000, 0b1000, 0b0011, 0b001>;
862-
defm : TLBI<"VAE2IS", 0b100, 0b1000, 0b0011, 0b001>;
863-
defm : TLBI<"VAE3IS", 0b110, 0b1000, 0b0011, 0b001>;
864-
defm : TLBI<"ASIDE1IS", 0b000, 0b1000, 0b0011, 0b010>;
865-
defm : TLBI<"VAAE1IS", 0b000, 0b1000, 0b0011, 0b011>;
866-
defm : TLBI<"ALLE1IS", 0b100, 0b1000, 0b0011, 0b100, 0>;
867-
defm : TLBI<"VALE1IS", 0b000, 0b1000, 0b0011, 0b101>;
868-
defm : TLBI<"VALE2IS", 0b100, 0b1000, 0b0011, 0b101>;
869-
defm : TLBI<"VALE3IS", 0b110, 0b1000, 0b0011, 0b101>;
870-
defm : TLBI<"VMALLS12E1IS", 0b100, 0b1000, 0b0011, 0b110, 0>;
871-
defm : TLBI<"VAALE1IS", 0b000, 0b1000, 0b0011, 0b111>;
872-
defm : TLBI<"IPAS2E1", 0b100, 0b1000, 0b0100, 0b001>;
873-
defm : TLBI<"IPAS2LE1", 0b100, 0b1000, 0b0100, 0b101>;
874-
defm : TLBI<"VMALLE1", 0b000, 0b1000, 0b0111, 0b000, 0>;
875-
defm : TLBI<"ALLE2", 0b100, 0b1000, 0b0111, 0b000, 0>;
876-
defm : TLBI<"ALLE3", 0b110, 0b1000, 0b0111, 0b000, 0>;
877-
defm : TLBI<"VAE1", 0b000, 0b1000, 0b0111, 0b001>;
878-
defm : TLBI<"VAE2", 0b100, 0b1000, 0b0111, 0b001>;
879-
defm : TLBI<"VAE3", 0b110, 0b1000, 0b0111, 0b001>;
880-
defm : TLBI<"ASIDE1", 0b000, 0b1000, 0b0111, 0b010>;
881-
defm : TLBI<"VAAE1", 0b000, 0b1000, 0b0111, 0b011>;
882-
defm : TLBI<"ALLE1", 0b100, 0b1000, 0b0111, 0b100, 0>;
883-
defm : TLBI<"VALE1", 0b000, 0b1000, 0b0111, 0b101>;
884-
defm : TLBI<"VALE2", 0b100, 0b1000, 0b0111, 0b101>;
885-
defm : TLBI<"VALE3", 0b110, 0b1000, 0b0111, 0b101>;
886-
defm : TLBI<"VMALLS12E1", 0b100, 0b1000, 0b0111, 0b110, 0>;
887-
defm : TLBI<"VAALE1", 0b000, 0b1000, 0b0111, 0b111>;
874+
// hasTLBIP op1 CRn CRm op2 needsreg
875+
defm : TLBI<"IPAS2E1IS", 1, 0b100, 0b1000, 0b0000, 0b001>;
876+
defm : TLBI<"IPAS2LE1IS", 1, 0b100, 0b1000, 0b0000, 0b101>;
877+
defm : TLBI<"VMALLE1IS", 0, 0b000, 0b1000, 0b0011, 0b000, 0>;
878+
defm : TLBI<"ALLE2IS", 0, 0b100, 0b1000, 0b0011, 0b000, 0>;
879+
defm : TLBI<"ALLE3IS", 0, 0b110, 0b1000, 0b0011, 0b000, 0>;
880+
defm : TLBI<"VAE1IS", 1, 0b000, 0b1000, 0b0011, 0b001>;
881+
defm : TLBI<"VAE2IS", 1, 0b100, 0b1000, 0b0011, 0b001>;
882+
defm : TLBI<"VAE3IS", 1, 0b110, 0b1000, 0b0011, 0b001>;
883+
defm : TLBI<"ASIDE1IS", 0, 0b000, 0b1000, 0b0011, 0b010>;
884+
defm : TLBI<"VAAE1IS", 1, 0b000, 0b1000, 0b0011, 0b011>;
885+
defm : TLBI<"ALLE1IS", 0, 0b100, 0b1000, 0b0011, 0b100, 0>;
886+
defm : TLBI<"VALE1IS", 1, 0b000, 0b1000, 0b0011, 0b101>;
887+
defm : TLBI<"VALE2IS", 1, 0b100, 0b1000, 0b0011, 0b101>;
888+
defm : TLBI<"VALE3IS", 1, 0b110, 0b1000, 0b0011, 0b101>;
889+
defm : TLBI<"VMALLS12E1IS", 0, 0b100, 0b1000, 0b0011, 0b110, 0>;
890+
defm : TLBI<"VAALE1IS", 1, 0b000, 0b1000, 0b0011, 0b111>;
891+
defm : TLBI<"IPAS2E1", 1, 0b100, 0b1000, 0b0100, 0b001>;
892+
defm : TLBI<"IPAS2LE1", 1, 0b100, 0b1000, 0b0100, 0b101>;
893+
defm : TLBI<"VMALLE1", 0, 0b000, 0b1000, 0b0111, 0b000, 0>;
894+
defm : TLBI<"ALLE2", 0, 0b100, 0b1000, 0b0111, 0b000, 0>;
895+
defm : TLBI<"ALLE3", 0, 0b110, 0b1000, 0b0111, 0b000, 0>;
896+
defm : TLBI<"VAE1", 1, 0b000, 0b1000, 0b0111, 0b001>;
897+
defm : TLBI<"VAE2", 1, 0b100, 0b1000, 0b0111, 0b001>;
898+
defm : TLBI<"VAE3", 1, 0b110, 0b1000, 0b0111, 0b001>;
899+
defm : TLBI<"ASIDE1", 0, 0b000, 0b1000, 0b0111, 0b010>;
900+
defm : TLBI<"VAAE1", 1, 0b000, 0b1000, 0b0111, 0b011>;
901+
defm : TLBI<"ALLE1", 0, 0b100, 0b1000, 0b0111, 0b100, 0>;
902+
defm : TLBI<"VALE1", 1, 0b000, 0b1000, 0b0111, 0b101>;
903+
defm : TLBI<"VALE2", 1, 0b100, 0b1000, 0b0111, 0b101>;
904+
defm : TLBI<"VALE3", 1, 0b110, 0b1000, 0b0111, 0b101>;
905+
defm : TLBI<"VMALLS12E1", 0, 0b100, 0b1000, 0b0111, 0b110, 0>;
906+
defm : TLBI<"VAALE1", 1, 0b000, 0b1000, 0b0111, 0b111>;
888907

889908
// Armv8.4-A Translation Lookaside Buffer Instructions (TLBI)
890909
let Requires = ["AArch64::FeatureTLB_RMI"] in {
891910
// Armv8.4-A Outer Sharable TLB Maintenance instructions:
892-
// op1 CRn CRm op2
893-
defm : TLBI<"VMALLE1OS", 0b000, 0b1000, 0b0001, 0b000, 0>;
894-
defm : TLBI<"VAE1OS", 0b000, 0b1000, 0b0001, 0b001>;
895-
defm : TLBI<"ASIDE1OS", 0b000, 0b1000, 0b0001, 0b010>;
896-
defm : TLBI<"VAAE1OS", 0b000, 0b1000, 0b0001, 0b011>;
897-
defm : TLBI<"VALE1OS", 0b000, 0b1000, 0b0001, 0b101>;
898-
defm : TLBI<"VAALE1OS", 0b000, 0b1000, 0b0001, 0b111>;
899-
defm : TLBI<"IPAS2E1OS", 0b100, 0b1000, 0b0100, 0b000>;
900-
defm : TLBI<"IPAS2LE1OS", 0b100, 0b1000, 0b0100, 0b100>;
901-
defm : TLBI<"VAE2OS", 0b100, 0b1000, 0b0001, 0b001>;
902-
defm : TLBI<"VALE2OS", 0b100, 0b1000, 0b0001, 0b101>;
903-
defm : TLBI<"VMALLS12E1OS", 0b100, 0b1000, 0b0001, 0b110, 0>;
904-
defm : TLBI<"VAE3OS", 0b110, 0b1000, 0b0001, 0b001>;
905-
defm : TLBI<"VALE3OS", 0b110, 0b1000, 0b0001, 0b101>;
906-
defm : TLBI<"ALLE2OS", 0b100, 0b1000, 0b0001, 0b000, 0>;
907-
defm : TLBI<"ALLE1OS", 0b100, 0b1000, 0b0001, 0b100, 0>;
908-
defm : TLBI<"ALLE3OS", 0b110, 0b1000, 0b0001, 0b000, 0>;
911+
// hasTLBIP op1 CRn CRm op2 needsreg
912+
defm : TLBI<"VMALLE1OS", 0, 0b000, 0b1000, 0b0001, 0b000, 0>;
913+
defm : TLBI<"VAE1OS", 1, 0b000, 0b1000, 0b0001, 0b001>;
914+
defm : TLBI<"ASIDE1OS", 0, 0b000, 0b1000, 0b0001, 0b010>;
915+
defm : TLBI<"VAAE1OS", 1, 0b000, 0b1000, 0b0001, 0b011>;
916+
defm : TLBI<"VALE1OS", 1, 0b000, 0b1000, 0b0001, 0b101>;
917+
defm : TLBI<"VAALE1OS", 1, 0b000, 0b1000, 0b0001, 0b111>;
918+
defm : TLBI<"IPAS2E1OS", 1, 0b100, 0b1000, 0b0100, 0b000>;
919+
defm : TLBI<"IPAS2LE1OS", 1, 0b100, 0b1000, 0b0100, 0b100>;
920+
defm : TLBI<"VAE2OS", 1, 0b100, 0b1000, 0b0001, 0b001>;
921+
defm : TLBI<"VALE2OS", 1, 0b100, 0b1000, 0b0001, 0b101>;
922+
defm : TLBI<"VMALLS12E1OS", 0, 0b100, 0b1000, 0b0001, 0b110, 0>;
923+
defm : TLBI<"VAE3OS", 1, 0b110, 0b1000, 0b0001, 0b001>;
924+
defm : TLBI<"VALE3OS", 1, 0b110, 0b1000, 0b0001, 0b101>;
925+
defm : TLBI<"ALLE2OS", 0, 0b100, 0b1000, 0b0001, 0b000, 0>;
926+
defm : TLBI<"ALLE1OS", 0, 0b100, 0b1000, 0b0001, 0b100, 0>;
927+
defm : TLBI<"ALLE3OS", 0, 0b110, 0b1000, 0b0001, 0b000, 0>;
909928

910929
// Armv8.4-A TLB Range Maintenance instructions:
911-
// op1 CRn CRm op2
912-
defm : TLBI<"RVAE1", 0b000, 0b1000, 0b0110, 0b001>;
913-
defm : TLBI<"RVAAE1", 0b000, 0b1000, 0b0110, 0b011>;
914-
defm : TLBI<"RVALE1", 0b000, 0b1000, 0b0110, 0b101>;
915-
defm : TLBI<"RVAALE1", 0b000, 0b1000, 0b0110, 0b111>;
916-
defm : TLBI<"RVAE1IS", 0b000, 0b1000, 0b0010, 0b001>;
917-
defm : TLBI<"RVAAE1IS", 0b000, 0b1000, 0b0010, 0b011>;
918-
defm : TLBI<"RVALE1IS", 0b000, 0b1000, 0b0010, 0b101>;
919-
defm : TLBI<"RVAALE1IS", 0b000, 0b1000, 0b0010, 0b111>;
920-
defm : TLBI<"RVAE1OS", 0b000, 0b1000, 0b0101, 0b001>;
921-
defm : TLBI<"RVAAE1OS", 0b000, 0b1000, 0b0101, 0b011>;
922-
defm : TLBI<"RVALE1OS", 0b000, 0b1000, 0b0101, 0b101>;
923-
defm : TLBI<"RVAALE1OS", 0b000, 0b1000, 0b0101, 0b111>;
924-
defm : TLBI<"RIPAS2E1IS", 0b100, 0b1000, 0b0000, 0b010>;
925-
defm : TLBI<"RIPAS2LE1IS", 0b100, 0b1000, 0b0000, 0b110>;
926-
defm : TLBI<"RIPAS2E1", 0b100, 0b1000, 0b0100, 0b010>;
927-
defm : TLBI<"RIPAS2LE1", 0b100, 0b1000, 0b0100, 0b110>;
928-
defm : TLBI<"RIPAS2E1OS", 0b100, 0b1000, 0b0100, 0b011>;
929-
defm : TLBI<"RIPAS2LE1OS", 0b100, 0b1000, 0b0100, 0b111>;
930-
defm : TLBI<"RVAE2", 0b100, 0b1000, 0b0110, 0b001>;
931-
defm : TLBI<"RVALE2", 0b100, 0b1000, 0b0110, 0b101>;
932-
defm : TLBI<"RVAE2IS", 0b100, 0b1000, 0b0010, 0b001>;
933-
defm : TLBI<"RVALE2IS", 0b100, 0b1000, 0b0010, 0b101>;
934-
defm : TLBI<"RVAE2OS", 0b100, 0b1000, 0b0101, 0b001>;
935-
defm : TLBI<"RVALE2OS", 0b100, 0b1000, 0b0101, 0b101>;
936-
defm : TLBI<"RVAE3", 0b110, 0b1000, 0b0110, 0b001>;
937-
defm : TLBI<"RVALE3", 0b110, 0b1000, 0b0110, 0b101>;
938-
defm : TLBI<"RVAE3IS", 0b110, 0b1000, 0b0010, 0b001>;
939-
defm : TLBI<"RVALE3IS", 0b110, 0b1000, 0b0010, 0b101>;
940-
defm : TLBI<"RVAE3OS", 0b110, 0b1000, 0b0101, 0b001>;
941-
defm : TLBI<"RVALE3OS", 0b110, 0b1000, 0b0101, 0b101>;
930+
// hasTLBIP op1 CRn CRm op2 needsreg
931+
defm : TLBI<"RVAE1", 1, 0b000, 0b1000, 0b0110, 0b001>;
932+
defm : TLBI<"RVAAE1", 1, 0b000, 0b1000, 0b0110, 0b011>;
933+
defm : TLBI<"RVALE1", 1, 0b000, 0b1000, 0b0110, 0b101>;
934+
defm : TLBI<"RVAALE1", 1, 0b000, 0b1000, 0b0110, 0b111>;
935+
defm : TLBI<"RVAE1IS", 1, 0b000, 0b1000, 0b0010, 0b001>;
936+
defm : TLBI<"RVAAE1IS", 1, 0b000, 0b1000, 0b0010, 0b011>;
937+
defm : TLBI<"RVALE1IS", 1, 0b000, 0b1000, 0b0010, 0b101>;
938+
defm : TLBI<"RVAALE1IS", 1, 0b000, 0b1000, 0b0010, 0b111>;
939+
defm : TLBI<"RVAE1OS", 1, 0b000, 0b1000, 0b0101, 0b001>;
940+
defm : TLBI<"RVAAE1OS", 1, 0b000, 0b1000, 0b0101, 0b011>;
941+
defm : TLBI<"RVALE1OS", 1, 0b000, 0b1000, 0b0101, 0b101>;
942+
defm : TLBI<"RVAALE1OS", 1, 0b000, 0b1000, 0b0101, 0b111>;
943+
defm : TLBI<"RIPAS2E1IS", 1, 0b100, 0b1000, 0b0000, 0b010>;
944+
defm : TLBI<"RIPAS2LE1IS", 1, 0b100, 0b1000, 0b0000, 0b110>;
945+
defm : TLBI<"RIPAS2E1", 1, 0b100, 0b1000, 0b0100, 0b010>;
946+
defm : TLBI<"RIPAS2LE1", 1, 0b100, 0b1000, 0b0100, 0b110>;
947+
defm : TLBI<"RIPAS2E1OS", 1, 0b100, 0b1000, 0b0100, 0b011>;
948+
defm : TLBI<"RIPAS2LE1OS", 1, 0b100, 0b1000, 0b0100, 0b111>;
949+
defm : TLBI<"RVAE2", 1, 0b100, 0b1000, 0b0110, 0b001>;
950+
defm : TLBI<"RVALE2", 1, 0b100, 0b1000, 0b0110, 0b101>;
951+
defm : TLBI<"RVAE2IS", 1, 0b100, 0b1000, 0b0010, 0b001>;
952+
defm : TLBI<"RVALE2IS", 1, 0b100, 0b1000, 0b0010, 0b101>;
953+
defm : TLBI<"RVAE2OS", 1, 0b100, 0b1000, 0b0101, 0b001>;
954+
defm : TLBI<"RVALE2OS", 1, 0b100, 0b1000, 0b0101, 0b101>;
955+
defm : TLBI<"RVAE3", 1, 0b110, 0b1000, 0b0110, 0b001>;
956+
defm : TLBI<"RVALE3", 1, 0b110, 0b1000, 0b0110, 0b101>;
957+
defm : TLBI<"RVAE3IS", 1, 0b110, 0b1000, 0b0010, 0b001>;
958+
defm : TLBI<"RVALE3IS", 1, 0b110, 0b1000, 0b0010, 0b101>;
959+
defm : TLBI<"RVAE3OS", 1, 0b110, 0b1000, 0b0101, 0b001>;
960+
defm : TLBI<"RVALE3OS", 1, 0b110, 0b1000, 0b0101, 0b101>;
942961
} //FeatureTLB_RMI
943962

944963
// Armv9-A Realm Management Extension TLBI Instructions
945964
let Requires = ["AArch64::FeatureRME"] in {
946-
defm : TLBI<"RPAOS", 0b110, 0b1000, 0b0100, 0b011>;
947-
defm : TLBI<"RPALOS", 0b110, 0b1000, 0b0100, 0b111>;
948-
defm : TLBI<"PAALLOS", 0b110, 0b1000, 0b0001, 0b100, 0>;
949-
defm : TLBI<"PAALL", 0b110, 0b1000, 0b0111, 0b100, 0>;
965+
defm : TLBI<"RPAOS", 0, 0b110, 0b1000, 0b0100, 0b011>;
966+
defm : TLBI<"RPALOS", 0, 0b110, 0b1000, 0b0100, 0b111>;
967+
defm : TLBI<"PAALLOS", 0, 0b110, 0b1000, 0b0001, 0b100, 0>;
968+
defm : TLBI<"PAALL", 0, 0b110, 0b1000, 0b0111, 0b100, 0>;
950969
}
951970

952971
// Armv9.5-A TLBI VMALL for Dirty State
953972
let Requires = ["AArch64::FeatureTLBIW"] in {
954-
// op1, CRn, CRm, op2, needsreg
955-
defm : TLBI<"VMALLWS2E1", 0b100, 0b1000, 0b0110, 0b010, 0>;
956-
defm : TLBI<"VMALLWS2E1IS", 0b100, 0b1000, 0b0010, 0b010, 0>;
957-
defm : TLBI<"VMALLWS2E1OS", 0b100, 0b1000, 0b0101, 0b010, 0>;
973+
// op1, CRn, CRm, op2, needsreg
974+
defm : TLBI<"VMALLWS2E1", 0, 0b100, 0b1000, 0b0110, 0b010, 0>;
975+
defm : TLBI<"VMALLWS2E1IS", 0, 0b100, 0b1000, 0b0010, 0b010, 0>;
976+
defm : TLBI<"VMALLWS2E1OS", 0, 0b100, 0b1000, 0b0101, 0b010, 0>;
958977
}
959978

960979
//===----------------------------------------------------------------------===//

‎llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp‎

Lines changed: 11 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -4020,23 +4020,23 @@ bool AArch64AsmParser::parseSyspAlias(StringRef Name, SMLoc NameLoc,
40204020
if (HasnXSQualifier) {
40214021
Op = Op.drop_back(3);
40224022
}
4023-
const AArch64TLBI::TLBI *TLBIorig = AArch64TLBI::lookupTLBIByName(Op);
4024-
if (!TLBIorig)
4023+
const AArch64TLBIP::TLBIP *TLBIPorig = AArch64TLBIP::lookupTLBIPByName(Op);
4024+
if (!TLBIPorig)
40254025
return TokError("invalid operand for TLBIP instruction");
4026-
const AArch64TLBI::TLBI TLBI(
4027-
TLBIorig->Name, TLBIorig->Encoding | (HasnXSQualifier ? (1 << 7) : 0),
4028-
TLBIorig->NeedsReg,
4026+
const AArch64TLBIP::TLBIP TLBIP(
4027+
TLBIPorig->Name, TLBIPorig->Encoding | (HasnXSQualifier ? (1 << 7) : 0),
4028+
TLBIPorig->NeedsReg,
40294029
HasnXSQualifier
4030-
? TLBIorig->FeaturesRequired | FeatureBitset({AArch64::FeatureXS})
4031-
: TLBIorig->FeaturesRequired);
4032-
if (!TLBI.haveFeatures(getSTI().getFeatureBits())) {
4030+
? TLBIPorig->FeaturesRequired | FeatureBitset({AArch64::FeatureXS})
4031+
: TLBIPorig->FeaturesRequired);
4032+
if (!TLBIP.haveFeatures(getSTI().getFeatureBits())) {
40334033
std::string Name =
4034-
std::string(TLBI.Name) + (HasnXSQualifier ? "nXS" : "");
4034+
std::string(TLBIP.Name) + (HasnXSQualifier ? "nXS" : "");
40354035
std::string Str("TLBIP " + Name + " requires: ");
4036-
setRequiredFeatureString(TLBI.getRequiredFeatures(), Str);
4036+
setRequiredFeatureString(TLBIP.getRequiredFeatures(), Str);
40374037
return TokError(Str);
40384038
}
4039-
createSysAlias(TLBI.Encoding, Operands, S);
4039+
createSysAlias(TLBIP.Encoding, Operands, S);
40404040
}
40414041

40424042
Lex(); // Eat operand.

‎llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp‎

Lines changed: 4 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1066,12 +1066,13 @@ bool AArch64InstPrinter::printSyspAlias(const MCInst *MI,
10661066
Encoding &= ~(1 << 7);
10671067
}
10681068

1069-
const AArch64TLBI::TLBI *TLBI = AArch64TLBI::lookupTLBIByEncoding(Encoding);
1070-
if (!TLBI || !TLBI->haveFeatures(STI.getFeatureBits()))
1069+
const AArch64TLBIP::TLBIP *TLBIP =
1070+
AArch64TLBIP::lookupTLBIPByEncoding(Encoding);
1071+
if (!TLBIP || !TLBIP->haveFeatures(STI.getFeatureBits()))
10711072
return false;
10721073

10731074
Ins = "tlbip\t";
1074-
Name = std::string(TLBI->Name);
1075+
Name = std::string(TLBIP->Name);
10751076
if (CnVal == 9)
10761077
Name += "nXS";
10771078
} else

‎llvm/lib/Target/AArch64/Utils/AArch64BaseInfo.cpp‎

Lines changed: 7 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -185,6 +185,13 @@ namespace llvm {
185185
}
186186
}
187187

188+
namespace llvm {
189+
namespace AArch64TLBIP {
190+
#define GET_TLBIPTable_IMPL
191+
#include "AArch64GenSystemOperands.inc"
192+
} // namespace AArch64TLBIP
193+
} // namespace llvm
194+
188195
namespace llvm {
189196
namespace AArch64SVCR {
190197
#define GET_SVCRsList_IMPL

‎llvm/lib/Target/AArch64/Utils/AArch64BaseInfo.h‎

Lines changed: 8 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -795,6 +795,14 @@ namespace AArch64TLBI {
795795
#include "AArch64GenSystemOperands.inc"
796796
}
797797

798+
namespace AArch64TLBIP {
799+
struct TLBIP : SysAliasReg {
800+
using SysAliasReg::SysAliasReg;
801+
};
802+
#define GET_TLBIPTable_DECL
803+
#include "AArch64GenSystemOperands.inc"
804+
} // namespace AArch64TLBIP
805+
798806
namespace AArch64II {
799807
/// Target Operand Flag enum.
800808
enum TOF {

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