Comments

Author: Pierre-vh

llvm/lib/Target/AMDGPU/SIISelLowering.cpp

@@ -17714,8 +17714,8 @@ atomicSupportedIfLegalIntType(const AtomicRMWInst *RMW) {
 /// Return if a flat address space atomicrmw can access private memory.
 static bool flatInstrMayAccessPrivate(const Instruction *I) {
   const MDNode *MD = I->getMetadata(LLVMContext::MD_noalias_addrspace);
-  return !(MD &&
-           AMDGPU::hasValueInRangeLikeMetadata(*MD, AMDGPUAS::PRIVATE_ADDRESS));
+  return !MD ||
+         !AMDGPU::hasValueInRangeLikeMetadata(*MD, AMDGPUAS::PRIVATE_ADDRESS);
 }
 
 TargetLowering::AtomicExpansionKind

llvm/lib/Target/AMDGPU/SIInstrInfo.cpp

@@ -4271,8 +4271,8 @@ bool SIInstrInfo::mayAccessScratchThroughFlat(const MachineInstr &MI) const {
     unsigned AS = Memop->getAddrSpace();
     if (AS == AMDGPUAS::FLAT_ADDRESS) {
       const MDNode *MD = Memop->getAAInfo().NoAliasAddrSpace;
-      return !(MD && AMDGPU::hasValueInRangeLikeMetadata(
-                         *MD, AMDGPUAS::PRIVATE_ADDRESS));
+      return !MD || !AMDGPU::hasValueInRangeLikeMetadata(
+                        *MD, AMDGPUAS::PRIVATE_ADDRESS);
     }
     return AS == AMDGPUAS::PRIVATE_ADDRESS;
   });