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5 files changed

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‎llvm/lib/Target/RISCV/RISCVISelLowering.cpp‎

Lines changed: 1 addition & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -5314,15 +5314,8 @@ static SDValue lowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG,
53145314
unsigned Index = 0;
53155315
if (ShuffleVectorInst::isDeInterleaveMaskOfFactor(Mask, Factor, Index) &&
53165316
1 < count_if(Mask, [](int Idx) { return Idx != -1; })) {
5317-
if (SDValue Src = getSingleShuffleSrc(VT, ContainerVT, V1, V2)) {
5318-
if (Src.getValueType() == VT) {
5319-
EVT WideVT = VT.getDoubleNumVectorElementsVT();
5320-
Src = DAG.getNode(ISD::INSERT_SUBVECTOR, DL, WideVT,
5321-
DAG.getUNDEF(WideVT), Src,
5322-
DAG.getVectorIdxConstant(0, DL));
5323-
}
5317+
if (SDValue Src = getSingleShuffleSrc(VT, ContainerVT, V1, V2))
53245318
return getDeinterleaveShiftAndTrunc(DL, VT, Src, Factor, Index, DAG);
5325-
}
53265319
}
53275320
}
53285321
}

‎llvm/test/CodeGen/RISCV/rvv/fixed-vectors-deinterleave-load.ll‎

Lines changed: 10 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -24,19 +24,20 @@ define {<16 x i1>, <16 x i1>} @vector_deinterleave_load_v16i1_v32i1(ptr %p) {
2424
; CHECK-NEXT: vadd.vi v12, v11, -16
2525
; CHECK-NEXT: vsetivli zero, 2, e8, mf4, ta, ma
2626
; CHECK-NEXT: vslidedown.vi v0, v8, 2
27-
; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu
27+
; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma
2828
; CHECK-NEXT: vadd.vi v11, v11, -15
2929
; CHECK-NEXT: vmerge.vim v13, v10, 1, v0
3030
; CHECK-NEXT: vmv1r.v v0, v8
31-
; CHECK-NEXT: vmerge.vim v14, v10, 1, v0
32-
; CHECK-NEXT: vnsrl.wi v8, v14, 0
31+
; CHECK-NEXT: vmerge.vim v8, v10, 1, v0
32+
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
33+
; CHECK-NEXT: vnsrl.wi v10, v8, 0
34+
; CHECK-NEXT: vnsrl.wi v8, v8, 8
3335
; CHECK-NEXT: vmv1r.v v0, v9
34-
; CHECK-NEXT: vrgather.vv v8, v13, v12, v0.t
35-
; CHECK-NEXT: vnsrl.wi v12, v14, 8
36-
; CHECK-NEXT: vmsne.vi v10, v8, 0
37-
; CHECK-NEXT: vrgather.vv v12, v13, v11, v0.t
38-
; CHECK-NEXT: vmsne.vi v8, v12, 0
39-
; CHECK-NEXT: vmv.v.v v0, v10
36+
; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu
37+
; CHECK-NEXT: vrgather.vv v10, v13, v12, v0.t
38+
; CHECK-NEXT: vrgather.vv v8, v13, v11, v0.t
39+
; CHECK-NEXT: vmsne.vi v0, v10, 0
40+
; CHECK-NEXT: vmsne.vi v8, v8, 0
4041
; CHECK-NEXT: ret
4142
%vec = load <32 x i1>, ptr %p
4243
%retval = call {<16 x i1>, <16 x i1>} @llvm.vector.deinterleave2.v32i1(<32 x i1> %vec)

‎llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-changes-length.ll‎

Lines changed: 2 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -104,7 +104,7 @@ define <4 x i32> @v4i32_v16i32(<16 x i32>) {
104104
; RV32-NEXT: vmv.v.i v0, 10
105105
; RV32-NEXT: vsetivli zero, 2, e16, m1, tu, ma
106106
; RV32-NEXT: vslideup.vi v14, v12, 1
107-
; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma
107+
; RV32-NEXT: vsetivli zero, 4, e32, m1, ta, ma
108108
; RV32-NEXT: vnsrl.wx v12, v8, a0
109109
; RV32-NEXT: vsetivli zero, 8, e32, m4, ta, ma
110110
; RV32-NEXT: vslidedown.vi v8, v8, 8
@@ -116,9 +116,8 @@ define <4 x i32> @v4i32_v16i32(<16 x i32>) {
116116
; RV64-LABEL: v4i32_v16i32:
117117
; RV64: # %bb.0:
118118
; RV64-NEXT: li a0, 32
119-
; RV64-NEXT: vsetivli zero, 1, e8, mf8, ta, ma
119+
; RV64-NEXT: vsetivli zero, 4, e32, m1, ta, ma
120120
; RV64-NEXT: vmv.v.i v0, 10
121-
; RV64-NEXT: vsetivli zero, 8, e32, m2, ta, ma
122121
; RV64-NEXT: vnsrl.wx v12, v8, a0
123122
; RV64-NEXT: vsetivli zero, 8, e32, m4, ta, ma
124123
; RV64-NEXT: vslidedown.vi v8, v8, 8

‎llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shufflevector-vnsrl.ll‎

Lines changed: 38 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -441,13 +441,25 @@ entry:
441441
}
442442

443443
define void @vnsrl_0_i8_single_src(ptr %in, ptr %out) {
444-
; CHECK-LABEL: vnsrl_0_i8_single_src:
445-
; CHECK: # %bb.0: # %entry
446-
; CHECK-NEXT: vsetivli zero, 8, e8, mf4, ta, ma
447-
; CHECK-NEXT: vle8.v v8, (a0)
448-
; CHECK-NEXT: vnsrl.wi v8, v8, 0
449-
; CHECK-NEXT: vse8.v v8, (a1)
450-
; CHECK-NEXT: ret
444+
; V-LABEL: vnsrl_0_i8_single_src:
445+
; V: # %bb.0: # %entry
446+
; V-NEXT: vsetivli zero, 8, e8, mf4, ta, ma
447+
; V-NEXT: vle8.v v8, (a0)
448+
; V-NEXT: vsetivli zero, 4, e8, mf8, ta, ma
449+
; V-NEXT: vnsrl.wi v8, v8, 0
450+
; V-NEXT: vsetivli zero, 8, e8, mf4, ta, ma
451+
; V-NEXT: vse8.v v8, (a1)
452+
; V-NEXT: ret
453+
;
454+
; ZVE32F-LABEL: vnsrl_0_i8_single_src:
455+
; ZVE32F: # %bb.0: # %entry
456+
; ZVE32F-NEXT: vsetivli zero, 8, e8, mf4, ta, ma
457+
; ZVE32F-NEXT: vle8.v v8, (a0)
458+
; ZVE32F-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
459+
; ZVE32F-NEXT: vnsrl.wi v8, v8, 0
460+
; ZVE32F-NEXT: vsetivli zero, 8, e8, mf4, ta, ma
461+
; ZVE32F-NEXT: vse8.v v8, (a1)
462+
; ZVE32F-NEXT: ret
451463
entry:
452464
%0 = load <8 x i8>, ptr %in, align 1
453465
%shuffle.i5 = shufflevector <8 x i8> %0, <8 x i8> poison, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 8, i32 10, i32 12, i32 14>
@@ -456,13 +468,25 @@ entry:
456468
}
457469

458470
define void @vnsrl_0_i8_single_src2(ptr %in, ptr %out) {
459-
; CHECK-LABEL: vnsrl_0_i8_single_src2:
460-
; CHECK: # %bb.0: # %entry
461-
; CHECK-NEXT: vsetivli zero, 8, e8, mf4, ta, ma
462-
; CHECK-NEXT: vle8.v v8, (a0)
463-
; CHECK-NEXT: vnsrl.wi v8, v8, 0
464-
; CHECK-NEXT: vse8.v v8, (a1)
465-
; CHECK-NEXT: ret
471+
; V-LABEL: vnsrl_0_i8_single_src2:
472+
; V: # %bb.0: # %entry
473+
; V-NEXT: vsetivli zero, 8, e8, mf4, ta, ma
474+
; V-NEXT: vle8.v v8, (a0)
475+
; V-NEXT: vsetivli zero, 4, e8, mf8, ta, ma
476+
; V-NEXT: vnsrl.wi v8, v8, 0
477+
; V-NEXT: vsetivli zero, 8, e8, mf4, ta, ma
478+
; V-NEXT: vse8.v v8, (a1)
479+
; V-NEXT: ret
480+
;
481+
; ZVE32F-LABEL: vnsrl_0_i8_single_src2:
482+
; ZVE32F: # %bb.0: # %entry
483+
; ZVE32F-NEXT: vsetivli zero, 8, e8, mf4, ta, ma
484+
; ZVE32F-NEXT: vle8.v v8, (a0)
485+
; ZVE32F-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
486+
; ZVE32F-NEXT: vnsrl.wi v8, v8, 0
487+
; ZVE32F-NEXT: vsetivli zero, 8, e8, mf4, ta, ma
488+
; ZVE32F-NEXT: vse8.v v8, (a1)
489+
; ZVE32F-NEXT: ret
466490
entry:
467491
%0 = load <8 x i8>, ptr %in, align 1
468492
%shuffle.i5 = shufflevector <8 x i8> %0, <8 x i8> poison, <8 x i32> <i32 0, i32 2, i32 4, i32 6, i32 undef, i32 undef, i32 undef, i32 undef>

‎llvm/test/CodeGen/RISCV/rvv/vector-deinterleave-fixed.ll‎

Lines changed: 9 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -19,18 +19,19 @@ define {<16 x i1>, <16 x i1>} @vector_deinterleave_v16i1_v32i1(<32 x i1> %vec) {
1919
; CHECK-NEXT: vsetvli zero, zero, e16, m2, ta, ma
2020
; CHECK-NEXT: vmv.s.x v9, a0
2121
; CHECK-NEXT: vmv1r.v v0, v8
22-
; CHECK-NEXT: vsetvli zero, zero, e8, m1, ta, mu
23-
; CHECK-NEXT: vmerge.vim v14, v10, 1, v0
24-
; CHECK-NEXT: vadd.vi v8, v12, -16
22+
; CHECK-NEXT: vsetvli zero, zero, e8, m1, ta, ma
23+
; CHECK-NEXT: vmerge.vim v8, v10, 1, v0
24+
; CHECK-NEXT: vadd.vi v10, v12, -16
2525
; CHECK-NEXT: vadd.vi v12, v12, -15
26-
; CHECK-NEXT: vnsrl.wi v10, v14, 0
26+
; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
27+
; CHECK-NEXT: vnsrl.wi v13, v8, 0
28+
; CHECK-NEXT: vnsrl.wi v8, v8, 8
2729
; CHECK-NEXT: vmv1r.v v0, v9
28-
; CHECK-NEXT: vrgather.vv v10, v11, v8, v0.t
29-
; CHECK-NEXT: vnsrl.wi v8, v14, 8
30-
; CHECK-NEXT: vmsne.vi v10, v10, 0
30+
; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, mu
31+
; CHECK-NEXT: vrgather.vv v13, v11, v10, v0.t
3132
; CHECK-NEXT: vrgather.vv v8, v11, v12, v0.t
33+
; CHECK-NEXT: vmsne.vi v0, v13, 0
3234
; CHECK-NEXT: vmsne.vi v8, v8, 0
33-
; CHECK-NEXT: vmv.v.v v0, v10
3435
; CHECK-NEXT: ret
3536
%retval = call {<16 x i1>, <16 x i1>} @llvm.vector.deinterleave2.v32i1(<32 x i1> %vec)
3637
ret {<16 x i1>, <16 x i1>} %retval

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