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Commit 26cb15c

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Refactor and remove unnecessary code
1 parent 454431b commit 26cb15c

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2 files changed

+7
-22
lines changed

2 files changed

+7
-22
lines changed

clang/lib/AST/ByteCode/InterpBuiltin.cpp

Lines changed: 1 addition & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -2877,9 +2877,6 @@ static bool interp__builtin_x86_extract_vector(InterpState &S, CodePtr OpPC,
28772877
unsigned SrcElems = Src.getNumElems();
28782878
unsigned DstElems = Dst.getNumElems();
28792879

2880-
if (SrcElems == 0 || DstElems == 0 || (SrcElems % DstElems) != 0)
2881-
return false;
2882-
28832880
unsigned NumLanes = SrcElems / DstElems;
28842881
unsigned Lane = static_cast<unsigned>(Index % NumLanes);
28852882
unsigned ExtractPos = Lane * DstElems;
@@ -2917,8 +2914,6 @@ static bool interp__builtin_x86_extract_vector_masked(InterpState &S, CodePtr Op
29172914

29182915
unsigned SrcElems = Src.getNumElems();
29192916
unsigned DstElems = Dst.getNumElems();
2920-
if (!SrcElems || !DstElems || (SrcElems % DstElems) != 0)
2921-
return false;
29222917

29232918
PrimType ElemT = Src.getFieldDesc()->getPrimType();
29242919
if (ElemT != Dst.getFieldDesc()->getPrimType() ||
@@ -2929,11 +2924,9 @@ static bool interp__builtin_x86_extract_vector_masked(InterpState &S, CodePtr Op
29292924
unsigned Lane = static_cast<unsigned>(ImmAPS.getZExtValue() % NumLanes);
29302925
unsigned Base = Lane * DstElems;
29312926

2932-
uint64_t Mask = MaskAPS.getZExtValue();
2933-
29342927
TYPE_SWITCH(ElemT, {
29352928
for (unsigned I = 0; I != DstElems; ++I) {
2936-
if ((Mask >> I) & 1)
2929+
if (MaskAPS[I])
29372930
Dst.elem<T>(I) = Src.elem<T>(Base + I);
29382931
else
29392932
Dst.elem<T>(I) = Merge.elem<T>(I);

clang/lib/AST/ExprConstant.cpp

Lines changed: 6 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -11787,13 +11787,8 @@ bool VectorExprEvaluator::VisitCallExpr(const CallExpr *E) {
1178711787
return false;
1178811788

1178911789
const auto *RetVT = E->getType()->castAs<VectorType>();
11790-
if (!RetVT) return false;
11791-
1179211790
unsigned RetLen = RetVT->getNumElements();
1179311791
unsigned SrcLen = SourceVec.getVectorLength();
11794-
if (SrcLen != RetLen * 2)
11795-
return false;
11796-
1179711792
unsigned Idx = SourceImm.getInt().getZExtValue() & 1;
1179811793

1179911794
SmallVector<APValue, 32> ResultElements;
@@ -11820,28 +11815,25 @@ bool VectorExprEvaluator::VisitCallExpr(const CallExpr *E) {
1182011815
APValue SourceVec, MergeVec;
1182111816
APSInt Imm, MaskImm;
1182211817

11823-
if (!EvaluateAsRValue(Info, E->getArg(0), SourceVec) ||
11824-
!EvaluateInteger(E->getArg(1), Imm, Info) ||
11825-
!EvaluateAsRValue(Info, E->getArg(2), MergeVec) ||
11826-
!EvaluateInteger(E->getArg(3), MaskImm, Info))
11827-
return false;
11818+
if (!EvaluateAsRValue(Info, E->getArg(0), SourceVec) ||
11819+
!EvaluateInteger(E->getArg(1), Imm, Info) ||
11820+
!EvaluateAsRValue(Info, E->getArg(2), MergeVec) ||
11821+
!EvaluateInteger(E->getArg(3), MaskImm, Info))
11822+
return false;
1182811823

1182911824
const auto *RetVT = E->getType()->castAs<VectorType>();
1183011825
unsigned RetLen = RetVT->getNumElements();
1183111826

1183211827
if (!SourceVec.isVector() || !MergeVec.isVector()) return false;
1183311828
unsigned SrcLen = SourceVec.getVectorLength();
11834-
if (!SrcLen || !RetLen || (SrcLen % RetLen) != 0) return false;
11835-
1183611829
unsigned Lanes = SrcLen / RetLen;
1183711830
unsigned Lane = static_cast<unsigned>(Imm.getZExtValue() % Lanes);
1183811831
unsigned Base = Lane * RetLen;
11839-
uint64_t Mask = MaskImm.getZExtValue();
1184011832

1184111833
SmallVector<APValue, 32> ResultElements;
1184211834
ResultElements.reserve(RetLen);
1184311835
for (unsigned I = 0; I < RetLen; ++I) {
11844-
if ((Mask >> I) & 1)
11836+
if (MaskImm[I])
1184511837
ResultElements.push_back(SourceVec.getVectorElt(Base + I));
1184611838
else
1184711839
ResultElements.push_back(MergeVec.getVectorElt(I));

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