@@ -3173,6 +3173,9 @@ class LLVM_ABI_FOR_TEST VPWidenMemoryRecipe : public VPRecipeBase,
31733173 : VPRecipeBase(SC, Operands, DL), VPIRMetadata(Metadata), Ingredient(I),
31743174 Consecutive (Consecutive), Reverse(Reverse) {
31753175 assert ((Consecutive || !Reverse) && " Reverse implies consecutive" );
3176+ assert (isa<VPVectorEndPointerRecipe>(getAddr ()) ||
3177+ !Reverse &&
3178+ " Reversed acccess without VPVectorEndPointerRecipe address?" );
31763179 }
31773180
31783181public:
@@ -3234,9 +3237,6 @@ struct LLVM_ABI_FOR_TEST VPWidenLoadRecipe final : public VPWidenMemoryRecipe,
32343237 : VPWidenMemoryRecipe(VPDef::VPWidenLoadSC, Load, {Addr}, Consecutive,
32353238 Reverse, Metadata, DL),
32363239 VPValue (this , &Load) {
3237- assert (isa<VPVectorEndPointerRecipe>(Addr) ||
3238- !Reverse &&
3239- " Reversed load without VPVectorEndPointerRecipe address?" );
32403240 setMask (Mask);
32413241 }
32423242
@@ -3316,9 +3316,6 @@ struct LLVM_ABI_FOR_TEST VPWidenStoreRecipe final : public VPWidenMemoryRecipe {
33163316 const VPIRMetadata &Metadata, DebugLoc DL)
33173317 : VPWidenMemoryRecipe(VPDef::VPWidenStoreSC, Store, {Addr, StoredVal},
33183318 Consecutive, Reverse, Metadata, DL) {
3319- assert (isa<VPVectorEndPointerRecipe>(Addr) ||
3320- !Reverse &&
3321- " Reversed store without VPVectorEndPointerRecipe address?" );
33223319 setMask (Mask);
33233320 }
33243321
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