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[AArch64]SIMD fpcvt codegen for rounding nodes (#165546)
This is followup patch to #157680, which allows simd fpcvt instructions to be generated from l/llround and l/llrint nodes.
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‎llvm/lib/Target/AArch64/AArch64InstrInfo.td‎

Lines changed: 43 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -6841,6 +6841,49 @@ defm : FPToIntegerPats<fp_to_uint, fp_to_uint_sat, fp_to_uint_sat_gi, ftrunc, "F
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defm : FPToIntegerPats<fp_to_sint, fp_to_sint_sat, fp_to_sint_sat_gi, fround, "FCVTAS">;
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defm : FPToIntegerPats<fp_to_uint, fp_to_uint_sat, fp_to_uint_sat_gi, fround, "FCVTAU">;
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6844+
let Predicates = [HasFPRCVT] in {
6845+
def : Pat<(f32 (bitconvert (i32 (any_lround f16:$Rn)))),
6846+
(FCVTASSHr f16:$Rn)>;
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def : Pat<(f64 (bitconvert (i64 (any_lround f16:$Rn)))),
6848+
(FCVTASDHr f16:$Rn)>;
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def : Pat<(f64 (bitconvert (i64 (any_llround f16:$Rn)))),
6850+
(FCVTASDHr f16:$Rn)>;
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def : Pat<(f64 (bitconvert (i64 (any_lround f32:$Rn)))),
6852+
(FCVTASDSr f32:$Rn)>;
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def : Pat<(f32 (bitconvert (i32 (any_lround f64:$Rn)))),
6854+
(FCVTASSDr f64:$Rn)>;
6855+
def : Pat<(f64 (bitconvert (i64 (any_llround f32:$Rn)))),
6856+
(FCVTASDSr f32:$Rn)>;
6857+
}
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def : Pat<(f32 (bitconvert (i32 (any_lround f32:$Rn)))),
6859+
(FCVTASv1i32 f32:$Rn)>;
6860+
def : Pat<(f64 (bitconvert (i64 (any_lround f64:$Rn)))),
6861+
(FCVTASv1i64 f64:$Rn)>;
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def : Pat<(f64 (bitconvert (i64 (any_llround f64:$Rn)))),
6863+
(FCVTASv1i64 f64:$Rn)>;
6864+
6865+
let Predicates = [HasFPRCVT] in {
6866+
def : Pat<(f32 (bitconvert (i32 (any_lrint f16:$Rn)))),
6867+
(FCVTZSSHr (FRINTXHr f16:$Rn))>;
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def : Pat<(f64 (bitconvert (i64 (any_lrint f16:$Rn)))),
6869+
(FCVTZSDHr (FRINTXHr f16:$Rn))>;
6870+
def : Pat<(f64 (bitconvert (i64 (any_llrint f16:$Rn)))),
6871+
(FCVTZSDHr (FRINTXHr f16:$Rn))>;
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def : Pat<(f64 (bitconvert (i64 (any_lrint f32:$Rn)))),
6873+
(FCVTZSDSr (FRINTXSr f32:$Rn))>;
6874+
def : Pat<(f32 (bitconvert (i32 (any_lrint f64:$Rn)))),
6875+
(FCVTZSSDr (FRINTXDr f64:$Rn))>;
6876+
def : Pat<(f64 (bitconvert (i64 (any_llrint f32:$Rn)))),
6877+
(FCVTZSDSr (FRINTXSr f32:$Rn))>;
6878+
}
6879+
def : Pat<(f32 (bitconvert (i32 (any_lrint f32:$Rn)))),
6880+
(FCVTZSv1i32 (FRINTXSr f32:$Rn))>;
6881+
def : Pat<(f64 (bitconvert (i64 (any_lrint f64:$Rn)))),
6882+
(FCVTZSv1i64 (FRINTXDr f64:$Rn))>;
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def : Pat<(f64 (bitconvert (i64 (any_llrint f64:$Rn)))),
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(FCVTZSv1i64 (FRINTXDr f64:$Rn))>;
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// f16 -> s16 conversions
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let Predicates = [HasFullFP16] in {
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def : Pat<(i16(fp_to_sint_sat_gi f16:$Rn)), (FCVTZSv1f16 f16:$Rn)>;

‎llvm/test/CodeGen/AArch64/arm64-cvt-simd-round-rint-strictfp.ll‎

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@@ -0,0 +1,286 @@
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
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; RUN: llc < %s -mtriple aarch64-unknown-unknown -mattr=+fprcvt,+fullfp16 | FileCheck %s --check-prefixes=CHECK,CHECK-FPRCVT
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; RUN: llc < %s -mtriple aarch64-unknown-unknown -mattr=+fullfp16 | FileCheck %s --check-prefixes=CHECK,CHECK-NOFPRCVT
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;
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; Lround strictfp
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;
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define float @lround_i32_f16_simd_exp(half %x) {
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; CHECK-FPRCVT-LABEL: lround_i32_f16_simd_exp:
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; CHECK-FPRCVT: // %bb.0:
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; CHECK-FPRCVT-NEXT: fcvtas s0, h0
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; CHECK-FPRCVT-NEXT: ret
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;
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; CHECK-NOFPRCVT-LABEL: lround_i32_f16_simd_exp:
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; CHECK-NOFPRCVT: // %bb.0:
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; CHECK-NOFPRCVT-NEXT: fcvtas w8, h0
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; CHECK-NOFPRCVT-NEXT: fmov s0, w8
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; CHECK-NOFPRCVT-NEXT: ret
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%val = call i32 @llvm.experimental.constrained.lround.i32.f16(half %x, metadata !"fpexcept.strict")
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%sum = bitcast i32 %val to float
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ret float %sum
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}
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define float @lround_i32_f32_simd_exp(float %x) {
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; CHECK-LABEL: lround_i32_f32_simd_exp:
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; CHECK: // %bb.0:
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; CHECK-NEXT: fcvtas s0, s0
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; CHECK-NEXT: ret
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%val = call i32 @llvm.experimental.constrained.lround.i32.f32(float %x, metadata !"fpexcept.strict")
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%bc = bitcast i32 %val to float
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ret float %bc
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}
34+
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define float @lround_i32_f64_simd_exp(double %x) {
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; CHECK-FPRCVT-LABEL: lround_i32_f64_simd_exp:
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; CHECK-FPRCVT: // %bb.0:
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; CHECK-FPRCVT-NEXT: fcvtas s0, d0
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; CHECK-FPRCVT-NEXT: ret
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;
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; CHECK-NOFPRCVT-LABEL: lround_i32_f64_simd_exp:
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; CHECK-NOFPRCVT: // %bb.0:
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; CHECK-NOFPRCVT-NEXT: fcvtas w8, d0
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; CHECK-NOFPRCVT-NEXT: fmov s0, w8
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; CHECK-NOFPRCVT-NEXT: ret
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%val = call i32 @llvm.experimental.constrained.lround.i32.f64(double %x, metadata !"fpexcept.strict")
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%bc = bitcast i32 %val to float
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ret float %bc
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}
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define double @lround_i64_f16_simd_exp(half %x) {
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; CHECK-FPRCVT-LABEL: lround_i64_f16_simd_exp:
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; CHECK-FPRCVT: // %bb.0:
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; CHECK-FPRCVT-NEXT: fcvtas d0, h0
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; CHECK-FPRCVT-NEXT: ret
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;
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; CHECK-NOFPRCVT-LABEL: lround_i64_f16_simd_exp:
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; CHECK-NOFPRCVT: // %bb.0:
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; CHECK-NOFPRCVT-NEXT: fcvtas x8, h0
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; CHECK-NOFPRCVT-NEXT: fmov d0, x8
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; CHECK-NOFPRCVT-NEXT: ret
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%val = call i64 @llvm.experimental.constrained.lround.i64.f16(half %x, metadata !"fpexcept.strict")
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%bc = bitcast i64 %val to double
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ret double %bc
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}
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define double @lround_i64_f32_simd_exp(float %x) {
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; CHECK-FPRCVT-LABEL: lround_i64_f32_simd_exp:
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; CHECK-FPRCVT: // %bb.0:
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; CHECK-FPRCVT-NEXT: fcvtas d0, s0
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; CHECK-FPRCVT-NEXT: ret
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;
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; CHECK-NOFPRCVT-LABEL: lround_i64_f32_simd_exp:
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; CHECK-NOFPRCVT: // %bb.0:
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; CHECK-NOFPRCVT-NEXT: fcvtas x8, s0
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; CHECK-NOFPRCVT-NEXT: fmov d0, x8
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; CHECK-NOFPRCVT-NEXT: ret
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%val = call i64 @llvm.experimental.constrained.lround.i64.f32(float %x, metadata !"fpexcept.strict")
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%bc = bitcast i64 %val to double
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ret double %bc
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}
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define double @lround_i64_f64_simd_exp(double %x) {
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; CHECK-LABEL: lround_i64_f64_simd_exp:
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; CHECK: // %bb.0:
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; CHECK-NEXT: fcvtas d0, d0
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; CHECK-NEXT: ret
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%val = call i64 @llvm.experimental.constrained.lround.i64.f64(double %x, metadata !"fpexcept.strict")
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%bc = bitcast i64 %val to double
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ret double %bc
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}
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;
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; Llround strictfp
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;
96+
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define double @llround_i64_f16_simd_exp(half %x) {
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; CHECK-FPRCVT-LABEL: llround_i64_f16_simd_exp:
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; CHECK-FPRCVT: // %bb.0:
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; CHECK-FPRCVT-NEXT: fcvtas d0, h0
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; CHECK-FPRCVT-NEXT: ret
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;
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; CHECK-NOFPRCVT-LABEL: llround_i64_f16_simd_exp:
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; CHECK-NOFPRCVT: // %bb.0:
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; CHECK-NOFPRCVT-NEXT: fcvtas x8, h0
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; CHECK-NOFPRCVT-NEXT: fmov d0, x8
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; CHECK-NOFPRCVT-NEXT: ret
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%val = call i64 @llvm.experimental.constrained.llround.i64.f16(half %x, metadata !"fpexcept.strict")
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%sum = bitcast i64 %val to double
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ret double %sum
111+
}
112+
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define double @llround_i64_f32_simd_exp(float %x) {
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; CHECK-FPRCVT-LABEL: llround_i64_f32_simd_exp:
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; CHECK-FPRCVT: // %bb.0:
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; CHECK-FPRCVT-NEXT: fcvtas d0, s0
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; CHECK-FPRCVT-NEXT: ret
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;
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; CHECK-NOFPRCVT-LABEL: llround_i64_f32_simd_exp:
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; CHECK-NOFPRCVT: // %bb.0:
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; CHECK-NOFPRCVT-NEXT: fcvtas x8, s0
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; CHECK-NOFPRCVT-NEXT: fmov d0, x8
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; CHECK-NOFPRCVT-NEXT: ret
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%val = call i64 @llvm.experimental.constrained.llround.i64.f32(float %x, metadata !"fpexcept.strict")
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%bc = bitcast i64 %val to double
126+
ret double %bc
127+
}
128+
129+
define double @llround_i64_f64_simd_exp(double %x) {
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; CHECK-LABEL: llround_i64_f64_simd_exp:
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; CHECK: // %bb.0:
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; CHECK-NEXT: fcvtas d0, d0
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; CHECK-NEXT: ret
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%val = call i64 @llvm.experimental.constrained.llround.i64.f64(double %x, metadata !"fpexcept.strict")
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%bc = bitcast i64 %val to double
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ret double %bc
137+
}
138+
139+
;
140+
; Lrint strictfp
141+
;
142+
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define float @lrint_i32_f16_simd_exp(half %x) {
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; CHECK-FPRCVT-LABEL: lrint_i32_f16_simd_exp:
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; CHECK-FPRCVT: // %bb.0:
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; CHECK-FPRCVT-NEXT: frintx h0, h0
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; CHECK-FPRCVT-NEXT: fcvtzs s0, h0
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; CHECK-FPRCVT-NEXT: ret
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;
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; CHECK-NOFPRCVT-LABEL: lrint_i32_f16_simd_exp:
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; CHECK-NOFPRCVT: // %bb.0:
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; CHECK-NOFPRCVT-NEXT: frintx h0, h0
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; CHECK-NOFPRCVT-NEXT: fcvtzs w8, h0
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; CHECK-NOFPRCVT-NEXT: fmov s0, w8
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; CHECK-NOFPRCVT-NEXT: ret
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%val = call i32 @llvm.experimental.constrained.lrint.i32.f16(half %x, metadata !"round.tonearest", metadata !"fpexcept.strict")
157+
%sum = bitcast i32 %val to float
158+
ret float %sum
159+
}
160+
161+
define float @lrint_i32_f32_simd_exp(float %x) {
162+
; CHECK-LABEL: lrint_i32_f32_simd_exp:
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; CHECK: // %bb.0:
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; CHECK-NEXT: frintx s0, s0
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; CHECK-NEXT: fcvtzs s0, s0
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; CHECK-NEXT: ret
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%val = call i32 @llvm.experimental.constrained.lrint.i32.f32(float %x, metadata !"round.tonearest", metadata !"fpexcept.strict")
168+
%bc = bitcast i32 %val to float
169+
ret float %bc
170+
}
171+
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define float @lrint_i32_f64_simd_exp(double %x) {
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; CHECK-FPRCVT-LABEL: lrint_i32_f64_simd_exp:
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; CHECK-FPRCVT: // %bb.0:
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; CHECK-FPRCVT-NEXT: frintx d0, d0
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; CHECK-FPRCVT-NEXT: fcvtzs s0, d0
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; CHECK-FPRCVT-NEXT: ret
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;
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; CHECK-NOFPRCVT-LABEL: lrint_i32_f64_simd_exp:
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; CHECK-NOFPRCVT: // %bb.0:
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; CHECK-NOFPRCVT-NEXT: frintx d0, d0
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; CHECK-NOFPRCVT-NEXT: fcvtzs w8, d0
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; CHECK-NOFPRCVT-NEXT: fmov s0, w8
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; CHECK-NOFPRCVT-NEXT: ret
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%val = call i32 @llvm.experimental.constrained.lrint.i32.f64(double %x, metadata !"round.tonearest", metadata !"fpexcept.strict")
186+
%bc = bitcast i32 %val to float
187+
ret float %bc
188+
}
189+
190+
define double @lrint_i64_f16_simd_exp(half %x) {
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; CHECK-FPRCVT-LABEL: lrint_i64_f16_simd_exp:
192+
; CHECK-FPRCVT: // %bb.0:
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; CHECK-FPRCVT-NEXT: frintx h0, h0
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; CHECK-FPRCVT-NEXT: fcvtzs d0, h0
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; CHECK-FPRCVT-NEXT: ret
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;
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; CHECK-NOFPRCVT-LABEL: lrint_i64_f16_simd_exp:
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; CHECK-NOFPRCVT: // %bb.0:
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; CHECK-NOFPRCVT-NEXT: frintx h0, h0
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; CHECK-NOFPRCVT-NEXT: fcvtzs x8, h0
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; CHECK-NOFPRCVT-NEXT: fmov d0, x8
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; CHECK-NOFPRCVT-NEXT: ret
203+
%val = call i64 @llvm.experimental.constrained.lrint.i53.f16(half %x, metadata !"round.tonearest", metadata !"fpexcept.strict")
204+
%bc = bitcast i64 %val to double
205+
ret double %bc
206+
}
207+
208+
define double @lrint_i64_f32_simd_exp(float %x) {
209+
; CHECK-FPRCVT-LABEL: lrint_i64_f32_simd_exp:
210+
; CHECK-FPRCVT: // %bb.0:
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; CHECK-FPRCVT-NEXT: frintx s0, s0
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; CHECK-FPRCVT-NEXT: fcvtzs d0, s0
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; CHECK-FPRCVT-NEXT: ret
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;
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; CHECK-NOFPRCVT-LABEL: lrint_i64_f32_simd_exp:
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; CHECK-NOFPRCVT: // %bb.0:
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; CHECK-NOFPRCVT-NEXT: frintx s0, s0
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; CHECK-NOFPRCVT-NEXT: fcvtzs x8, s0
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; CHECK-NOFPRCVT-NEXT: fmov d0, x8
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; CHECK-NOFPRCVT-NEXT: ret
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%val = call i64 @llvm.experimental.constrained.lrint.i64.f32(float %x, metadata !"round.tonearest", metadata !"fpexcept.strict")
222+
%bc = bitcast i64 %val to double
223+
ret double %bc
224+
}
225+
226+
define double @lrint_i64_f64_simd_exp(double %x) {
227+
; CHECK-LABEL: lrint_i64_f64_simd_exp:
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; CHECK: // %bb.0:
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; CHECK-NEXT: frintx d0, d0
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; CHECK-NEXT: fcvtzs d0, d0
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; CHECK-NEXT: ret
232+
%val = call i64 @llvm.experimental.constrained.lrint.i64.f64(double %x, metadata !"round.tonearest", metadata !"fpexcept.strict")
233+
%bc = bitcast i64 %val to double
234+
ret double %bc
235+
}
236+
237+
;
238+
; Llrint strictfp
239+
;
240+
241+
define double @llrint_i64_f16_simd_exp(half %x) {
242+
; CHECK-FPRCVT-LABEL: llrint_i64_f16_simd_exp:
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; CHECK-FPRCVT: // %bb.0:
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; CHECK-FPRCVT-NEXT: frintx h0, h0
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; CHECK-FPRCVT-NEXT: fcvtzs d0, h0
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; CHECK-FPRCVT-NEXT: ret
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;
248+
; CHECK-NOFPRCVT-LABEL: llrint_i64_f16_simd_exp:
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; CHECK-NOFPRCVT: // %bb.0:
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; CHECK-NOFPRCVT-NEXT: frintx h0, h0
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; CHECK-NOFPRCVT-NEXT: fcvtzs x8, h0
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; CHECK-NOFPRCVT-NEXT: fmov d0, x8
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; CHECK-NOFPRCVT-NEXT: ret
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%val = call i64 @llvm.experimental.constrained.llrint.i64.f16(half %x, metadata !"round.tonearest", metadata !"fpexcept.strict")
255+
%sum = bitcast i64 %val to double
256+
ret double %sum
257+
}
258+
259+
define double @llrint_i64_f32_simd_exp(float %x) {
260+
; CHECK-FPRCVT-LABEL: llrint_i64_f32_simd_exp:
261+
; CHECK-FPRCVT: // %bb.0:
262+
; CHECK-FPRCVT-NEXT: frintx s0, s0
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; CHECK-FPRCVT-NEXT: fcvtzs d0, s0
264+
; CHECK-FPRCVT-NEXT: ret
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;
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; CHECK-NOFPRCVT-LABEL: llrint_i64_f32_simd_exp:
267+
; CHECK-NOFPRCVT: // %bb.0:
268+
; CHECK-NOFPRCVT-NEXT: frintx s0, s0
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; CHECK-NOFPRCVT-NEXT: fcvtzs x8, s0
270+
; CHECK-NOFPRCVT-NEXT: fmov d0, x8
271+
; CHECK-NOFPRCVT-NEXT: ret
272+
%val = call i64 @llvm.experimental.constrained.llrint.i64.f32(float %x, metadata !"round.tonearest", metadata !"fpexcept.strict")
273+
%bc = bitcast i64 %val to double
274+
ret double %bc
275+
}
276+
277+
define double @llrint_i64_f64_simd_exp(double %x) {
278+
; CHECK-LABEL: llrint_i64_f64_simd_exp:
279+
; CHECK: // %bb.0:
280+
; CHECK-NEXT: frintx d0, d0
281+
; CHECK-NEXT: fcvtzs d0, d0
282+
; CHECK-NEXT: ret
283+
%val = call i64 @llvm.experimental.constrained.llrint.i64.f64(double %x, metadata !"round.tonearest", metadata !"fpexcept.strict")
284+
%bc = bitcast i64 %val to double
285+
ret double %bc
286+
}

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