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lialanlialan
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[GISel][AMDGPU] Expand ShuffleVector (#124527)
This patch dismantles G_SHUFFLE_VECTOR before lowering. The original lowering would emit extract vector element ops. We found that by using unmerged values the build vector op combine could find ways to fold. Only enabled on AMDGPU. This resolves #123631
1 parent 75cbb1f commit 2795abb

21 files changed

+2358
-8059
lines changed

‎llvm/include/llvm/CodeGen/GlobalISel/CombinerHelper.h

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -261,6 +261,10 @@ class CombinerHelper {
261261
void applyCombineShuffleConcat(MachineInstr &MI,
262262
SmallVector<Register> &Ops) const;
263263

264+
/// Replace \p MI with a build_vector.
265+
bool matchCombineShuffleToBuildVector(MachineInstr &MI) const;
266+
void applyCombineShuffleToBuildVector(MachineInstr &MI) const;
267+
264268
/// Try to combine G_SHUFFLE_VECTOR into G_CONCAT_VECTORS.
265269
/// Returns true if MI changed.
266270
///

‎llvm/include/llvm/Target/GlobalISel/Combine.td

Lines changed: 7 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1571,6 +1571,13 @@ def combine_shuffle_concat : GICombineRule<
15711571
[{ return Helper.matchCombineShuffleConcat(*${root}, ${matchinfo}); }]),
15721572
(apply [{ Helper.applyCombineShuffleConcat(*${root}, ${matchinfo}); }])>;
15731573

1574+
// Combines shuffles of vector into build_vector
1575+
def combine_shuffle_vector_to_build_vector : GICombineRule<
1576+
(defs root:$root),
1577+
(match (G_SHUFFLE_VECTOR $dst, $src1, $src2, $mask):$root,
1578+
[{ return Helper.matchCombineShuffleToBuildVector(*${root}); }]),
1579+
(apply [{ Helper.applyCombineShuffleToBuildVector(*${root}); }])>;
1580+
15741581
def insert_vector_element_idx_undef : GICombineRule<
15751582
(defs root:$root),
15761583
(match (G_IMPLICIT_DEF $idx),

‎llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp

Lines changed: 40 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -25,6 +25,7 @@
2525
#include "llvm/CodeGen/MachineInstr.h"
2626
#include "llvm/CodeGen/MachineMemOperand.h"
2727
#include "llvm/CodeGen/MachineRegisterInfo.h"
28+
#include "llvm/CodeGen/Register.h"
2829
#include "llvm/CodeGen/RegisterBankInfo.h"
2930
#include "llvm/CodeGen/TargetInstrInfo.h"
3031
#include "llvm/CodeGen/TargetLowering.h"
@@ -385,6 +386,45 @@ void CombinerHelper::applyCombineConcatVectors(
385386
MI.eraseFromParent();
386387
}
387388

389+
bool CombinerHelper::matchCombineShuffleToBuildVector(MachineInstr &MI) const {
390+
assert(MI.getOpcode() == TargetOpcode::G_SHUFFLE_VECTOR &&
391+
"Invalid instruction");
392+
auto &Shuffle = cast<GShuffleVector>(MI);
393+
394+
Register SrcVec1 = Shuffle.getSrc1Reg();
395+
Register SrcVec2 = Shuffle.getSrc2Reg();
396+
397+
LLT SrcVec1Type = MRI.getType(SrcVec1);
398+
LLT SrcVec2Type = MRI.getType(SrcVec2);
399+
return SrcVec1Type.isVector() && SrcVec2Type.isVector();
400+
}
401+
402+
void CombinerHelper::applyCombineShuffleToBuildVector(MachineInstr &MI) const {
403+
auto &Shuffle = cast<GShuffleVector>(MI);
404+
405+
Register SrcVec1 = Shuffle.getSrc1Reg();
406+
Register SrcVec2 = Shuffle.getSrc2Reg();
407+
LLT EltTy = MRI.getType(SrcVec1).getElementType();
408+
int Width = MRI.getType(SrcVec1).getNumElements();
409+
410+
auto Unmerge1 = Builder.buildUnmerge(EltTy, SrcVec1);
411+
auto Unmerge2 = Builder.buildUnmerge(EltTy, SrcVec2);
412+
413+
SmallVector<Register> Extracts;
414+
// Select only applicable elements from unmerged values.
415+
for (int Val : Shuffle.getMask()) {
416+
if (Val == -1)
417+
Extracts.push_back(Builder.buildUndef(EltTy).getReg(0));
418+
else if (Val < Width)
419+
Extracts.push_back(Unmerge1.getReg(Val));
420+
else
421+
Extracts.push_back(Unmerge2.getReg(Val - Width));
422+
}
423+
424+
Builder.buildBuildVector(MI.getOperand(0).getReg(), Extracts);
425+
MI.eraseFromParent();
426+
}
427+
388428
bool CombinerHelper::matchCombineShuffleConcat(
389429
MachineInstr &MI, SmallVector<Register> &Ops) const {
390430
ArrayRef<int> Mask = MI.getOperand(3).getShuffleMask();

‎llvm/lib/Target/AMDGPU/AMDGPUCombine.td

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -163,7 +163,8 @@ def gfx8_combines : GICombineGroup<[expand_promoted_fmed3]>;
163163

164164
def AMDGPUPreLegalizerCombiner: GICombiner<
165165
"AMDGPUPreLegalizerCombinerImpl",
166-
[all_combines, combine_fmul_with_select_to_fldexp, clamp_i64_to_i16, foldable_fneg]> {
166+
[all_combines, combine_fmul_with_select_to_fldexp, clamp_i64_to_i16,
167+
foldable_fneg, combine_shuffle_vector_to_build_vector]> {
167168
let CombineAllMethodName = "tryCombineAllImpl";
168169
}
169170

‎llvm/test/CodeGen/AMDGPU/GlobalISel/prelegalizer-combiner-shuffle.mir

Lines changed: 137 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,137 @@
1+
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2+
# RUN: llc -global-isel -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -run-pass=amdgpu-prelegalizer-combiner -verify-machineinstrs -o - %s | FileCheck %s
3+
4+
---
5+
name: shuffle_vector_to_extract
6+
tracksRegLiveness: true
7+
body: |
8+
bb.0:
9+
liveins: $vgpr0, $vgpr1
10+
11+
; CHECK-LABEL: name: shuffle_vector_to_extract
12+
; CHECK: liveins: $vgpr0, $vgpr1
13+
; CHECK-NEXT: {{ $}}
14+
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
15+
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(p3) = COPY $vgpr1
16+
; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(<8 x s16>) = G_LOAD [[COPY]](p3) :: (load (<8 x s16>), align 8, addrspace 3)
17+
; CHECK-NEXT: [[UV:%[0-9]+]]:_(s16), [[UV1:%[0-9]+]]:_(s16), [[UV2:%[0-9]+]]:_(s16), [[UV3:%[0-9]+]]:_(s16), [[UV4:%[0-9]+]]:_(s16), [[UV5:%[0-9]+]]:_(s16), [[UV6:%[0-9]+]]:_(s16), [[UV7:%[0-9]+]]:_(s16) = G_UNMERGE_VALUES [[LOAD]](<8 x s16>)
18+
; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s16>) = G_BUILD_VECTOR [[UV4]](s16), [[UV5]](s16), [[UV6]](s16), [[UV7]](s16)
19+
; CHECK-NEXT: G_STORE [[BUILD_VECTOR]](<4 x s16>), [[COPY1]](p3) :: (store (<4 x s16>), addrspace 3)
20+
; CHECK-NEXT: SI_RETURN
21+
%0:_(p3) = COPY $vgpr0
22+
%1:_(p3) = COPY $vgpr1
23+
%12:_(<8 x s16>) = G_IMPLICIT_DEF
24+
%10:_(<8 x s16>) = G_LOAD %0(p3) :: (load (<8 x s16>), align 8, addrspace 3)
25+
%11:_(<4 x s16>) = G_SHUFFLE_VECTOR %10(<8 x s16>), %12, shufflemask(4, 5, 6, 7)
26+
G_STORE %11(<4 x s16>), %1(p3) :: (store (<4 x s16>), addrspace 3)
27+
SI_RETURN
28+
...
29+
30+
---
31+
name: shuffle_vector_to_extract2
32+
tracksRegLiveness: true
33+
body: |
34+
bb.0:
35+
liveins: $vgpr0, $vgpr1
36+
37+
; CHECK-LABEL: name: shuffle_vector_to_extract2
38+
; CHECK: liveins: $vgpr0, $vgpr1
39+
; CHECK-NEXT: {{ $}}
40+
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
41+
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(p3) = COPY $vgpr1
42+
; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(<8 x s16>) = G_LOAD [[COPY]](p3) :: (load (<8 x s16>), align 8, addrspace 3)
43+
; CHECK-NEXT: [[UV:%[0-9]+]]:_(s16), [[UV1:%[0-9]+]]:_(s16), [[UV2:%[0-9]+]]:_(s16), [[UV3:%[0-9]+]]:_(s16), [[UV4:%[0-9]+]]:_(s16), [[UV5:%[0-9]+]]:_(s16), [[UV6:%[0-9]+]]:_(s16), [[UV7:%[0-9]+]]:_(s16) = G_UNMERGE_VALUES [[LOAD]](<8 x s16>)
44+
; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[UV3]](s16), [[UV4]](s16)
45+
; CHECK-NEXT: G_STORE [[BUILD_VECTOR]](<2 x s16>), [[COPY1]](p3) :: (store (<2 x s16>), addrspace 3)
46+
; CHECK-NEXT: SI_RETURN
47+
%0:_(p3) = COPY $vgpr0
48+
%1:_(p3) = COPY $vgpr1
49+
%12:_(<8 x s16>) = G_IMPLICIT_DEF
50+
%10:_(<8 x s16>) = G_LOAD %0(p3) :: (load (<8 x s16>), align 8, addrspace 3)
51+
%11:_(<2 x s16>) = G_SHUFFLE_VECTOR %10(<8 x s16>), %12, shufflemask(3, 4)
52+
G_STORE %11(<2 x s16>), %1(p3) :: (store (<2 x s16>), addrspace 3)
53+
SI_RETURN
54+
55+
...
56+
57+
---
58+
name: shuffle_vector_to_extract_odd_elements
59+
tracksRegLiveness: true
60+
body: |
61+
bb.0:
62+
liveins: $vgpr0, $vgpr1
63+
64+
; CHECK-LABEL: name: shuffle_vector_to_extract_odd_elements
65+
; CHECK: liveins: $vgpr0, $vgpr1
66+
; CHECK-NEXT: {{ $}}
67+
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
68+
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(p3) = COPY $vgpr1
69+
; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(<8 x s16>) = G_LOAD [[COPY]](p3) :: (load (<8 x s16>), align 8, addrspace 3)
70+
; CHECK-NEXT: [[UV:%[0-9]+]]:_(s16), [[UV1:%[0-9]+]]:_(s16), [[UV2:%[0-9]+]]:_(s16), [[UV3:%[0-9]+]]:_(s16), [[UV4:%[0-9]+]]:_(s16), [[UV5:%[0-9]+]]:_(s16), [[UV6:%[0-9]+]]:_(s16), [[UV7:%[0-9]+]]:_(s16) = G_UNMERGE_VALUES [[LOAD]](<8 x s16>)
71+
; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<3 x s16>) = G_BUILD_VECTOR [[UV]](s16), [[UV1]](s16), [[UV2]](s16)
72+
; CHECK-NEXT: G_STORE [[BUILD_VECTOR]](<3 x s16>), [[COPY1]](p3) :: (store (<3 x s16>), align 8, addrspace 3)
73+
; CHECK-NEXT: SI_RETURN
74+
%0:_(p3) = COPY $vgpr0
75+
%1:_(p3) = COPY $vgpr1
76+
%12:_(<8 x s16>) = G_IMPLICIT_DEF
77+
%10:_(<8 x s16>) = G_LOAD %0(p3) :: (load (<8 x s16>), align 8, addrspace 3)
78+
%11:_(<3 x s16>) = G_SHUFFLE_VECTOR %10(<8 x s16>), %12, shufflemask(0, 1, 2)
79+
G_STORE %11(<3 x s16>), %1(p3) :: (store (<3 x s16>), addrspace 3)
80+
SI_RETURN
81+
...
82+
83+
84+
---
85+
name: shuffle_vector_to_extract_minus_1_no_conversion
86+
tracksRegLiveness: true
87+
body: |
88+
bb.0:
89+
liveins: $vgpr0, $vgpr1
90+
91+
; CHECK-LABEL: name: shuffle_vector_to_extract_minus_1_no_conversion
92+
; CHECK: liveins: $vgpr0, $vgpr1
93+
; CHECK-NEXT: {{ $}}
94+
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
95+
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(p3) = COPY $vgpr1
96+
; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(<8 x s16>) = G_LOAD [[COPY]](p3) :: (load (<8 x s16>), align 8, addrspace 3)
97+
; CHECK-NEXT: [[UV:%[0-9]+]]:_(s16), [[UV1:%[0-9]+]]:_(s16), [[UV2:%[0-9]+]]:_(s16), [[UV3:%[0-9]+]]:_(s16), [[UV4:%[0-9]+]]:_(s16), [[UV5:%[0-9]+]]:_(s16), [[UV6:%[0-9]+]]:_(s16), [[UV7:%[0-9]+]]:_(s16) = G_UNMERGE_VALUES [[LOAD]](<8 x s16>)
98+
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
99+
; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s16>) = G_BUILD_VECTOR [[UV4]](s16), [[UV5]](s16), [[DEF]](s16), [[UV7]](s16)
100+
; CHECK-NEXT: G_STORE [[BUILD_VECTOR]](<4 x s16>), [[COPY1]](p3) :: (store (<4 x s16>), addrspace 3)
101+
; CHECK-NEXT: SI_RETURN
102+
%0:_(p3) = COPY $vgpr0
103+
%1:_(p3) = COPY $vgpr1
104+
%12:_(<8 x s16>) = G_IMPLICIT_DEF
105+
%10:_(<8 x s16>) = G_LOAD %0(p3) :: (load (<8 x s16>), align 8, addrspace 3)
106+
%11:_(<4 x s16>) = G_SHUFFLE_VECTOR %10(<8 x s16>), %12, shufflemask(4, 5, -1, 7)
107+
G_STORE %11(<4 x s16>), %1(p3) :: (store (<4 x s16>), addrspace 3)
108+
SI_RETURN
109+
...
110+
111+
---
112+
name: shuffle_vector_to_extract_across_vectors_no_conversion
113+
tracksRegLiveness: true
114+
body: |
115+
bb.0:
116+
liveins: $vgpr0, $vgpr1
117+
118+
; CHECK-LABEL: name: shuffle_vector_to_extract_across_vectors_no_conversion
119+
; CHECK: liveins: $vgpr0, $vgpr1
120+
; CHECK-NEXT: {{ $}}
121+
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p3) = COPY $vgpr0
122+
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(p3) = COPY $vgpr1
123+
; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(<8 x s16>) = G_LOAD [[COPY]](p3) :: (load (<8 x s16>), align 8, addrspace 3)
124+
; CHECK-NEXT: [[UV:%[0-9]+]]:_(s16), [[UV1:%[0-9]+]]:_(s16), [[UV2:%[0-9]+]]:_(s16), [[UV3:%[0-9]+]]:_(s16), [[UV4:%[0-9]+]]:_(s16), [[UV5:%[0-9]+]]:_(s16), [[UV6:%[0-9]+]]:_(s16), [[UV7:%[0-9]+]]:_(s16) = G_UNMERGE_VALUES [[LOAD]](<8 x s16>)
125+
; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
126+
; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s16>) = G_BUILD_VECTOR [[UV6]](s16), [[UV7]](s16), [[DEF]](s16), [[DEF]](s16)
127+
; CHECK-NEXT: G_STORE [[BUILD_VECTOR]](<4 x s16>), [[COPY1]](p3) :: (store (<4 x s16>), addrspace 3)
128+
; CHECK-NEXT: SI_RETURN
129+
%0:_(p3) = COPY $vgpr0
130+
%1:_(p3) = COPY $vgpr1
131+
%12:_(<8 x s16>) = G_IMPLICIT_DEF
132+
%10:_(<8 x s16>) = G_LOAD %0(p3) :: (load (<8 x s16>), align 8, addrspace 3)
133+
%11:_(<4 x s16>) = G_SHUFFLE_VECTOR %10(<8 x s16>), %12, shufflemask(6, 7, 8, 9)
134+
G_STORE %11(<4 x s16>), %1(p3) :: (store (<4 x s16>), addrspace 3)
135+
SI_RETURN
136+
...
137+

‎llvm/test/CodeGen/AMDGPU/GlobalISel/shufflevector.ll

Lines changed: 18 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,18 @@
1+
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2+
; RUN: llc -global-isel -march=amdgcn -mtriple=amdgcn-amd-hmcsa -mcpu=gfx942 -verify-machineinstrs < %s | FileCheck -check-prefix=GFX942 %s
3+
4+
define void @shuffle_to_extract(ptr addrspace(3) %in, ptr addrspace(3) %out) {
5+
; GFX942-LABEL: shuffle_to_extract:
6+
; GFX942: ; %bb.0:
7+
; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
8+
; GFX942-NEXT: ds_read2_b64 v[2:5], v0 offset1:1
9+
; GFX942-NEXT: s_waitcnt lgkmcnt(0)
10+
; GFX942-NEXT: ds_write_b64 v1, v[4:5]
11+
; GFX942-NEXT: s_waitcnt lgkmcnt(0)
12+
; GFX942-NEXT: s_setpc_b64 s[30:31]
13+
%val = load <8 x half>, ptr addrspace(3) %in, align 8
14+
%res = shufflevector <8 x half> %val, <8 x half> poison, <4 x i32> <i32 4, i32 5, i32 6, i32 7>
15+
store <4 x half> %res, ptr addrspace(3) %out, align 8
16+
ret void
17+
}
18+

‎llvm/test/CodeGen/AMDGPU/buffer-fat-pointers-contents-legalization.ll

Lines changed: 6 additions & 21 deletions
Original file line numberDiff line numberDiff line change
@@ -1736,10 +1736,6 @@ define <5 x i16> @load_v5i16(ptr addrspace(8) inreg %buf) {
17361736
; GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
17371737
; GISEL-NEXT: buffer_load_dwordx2 v[0:1], off, s[16:19], 0
17381738
; GISEL-NEXT: buffer_load_ushort v2, off, s[16:19], 0 offset:8
1739-
; GISEL-NEXT: s_mov_b32 s4, 0xffff
1740-
; GISEL-NEXT: s_waitcnt vmcnt(1)
1741-
; GISEL-NEXT: v_bfi_b32 v0, s4, v0, v0
1742-
; GISEL-NEXT: v_bfi_b32 v1, s4, v1, v1
17431739
; GISEL-NEXT: s_waitcnt vmcnt(0)
17441740
; GISEL-NEXT: s_setpc_b64 s[30:31]
17451741
%p = addrspacecast ptr addrspace(8) %buf to ptr addrspace(7)
@@ -1820,11 +1816,6 @@ define <7 x i16> @load_v7i16(ptr addrspace(8) inreg %buf) {
18201816
; GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
18211817
; GISEL-NEXT: buffer_load_dwordx3 v[0:2], off, s[16:19], 0
18221818
; GISEL-NEXT: buffer_load_ushort v3, off, s[16:19], 0 offset:12
1823-
; GISEL-NEXT: s_mov_b32 s4, 0xffff
1824-
; GISEL-NEXT: s_waitcnt vmcnt(1)
1825-
; GISEL-NEXT: v_bfi_b32 v0, s4, v0, v0
1826-
; GISEL-NEXT: v_bfi_b32 v1, s4, v1, v1
1827-
; GISEL-NEXT: v_bfi_b32 v2, s4, v2, v2
18281819
; GISEL-NEXT: s_waitcnt vmcnt(0)
18291820
; GISEL-NEXT: s_setpc_b64 s[30:31]
18301821
%p = addrspacecast ptr addrspace(8) %buf to ptr addrspace(7)
@@ -1867,12 +1858,6 @@ define <9 x i16> @load_v9i16(ptr addrspace(8) inreg %buf) {
18671858
; GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
18681859
; GISEL-NEXT: buffer_load_dwordx4 v[0:3], off, s[16:19], 0
18691860
; GISEL-NEXT: buffer_load_ushort v4, off, s[16:19], 0 offset:16
1870-
; GISEL-NEXT: s_mov_b32 s4, 0xffff
1871-
; GISEL-NEXT: s_waitcnt vmcnt(1)
1872-
; GISEL-NEXT: v_bfi_b32 v0, s4, v0, v0
1873-
; GISEL-NEXT: v_bfi_b32 v1, s4, v1, v1
1874-
; GISEL-NEXT: v_bfi_b32 v2, s4, v2, v2
1875-
; GISEL-NEXT: v_bfi_b32 v3, s4, v3, v3
18761861
; GISEL-NEXT: s_waitcnt vmcnt(0)
18771862
; GISEL-NEXT: s_setpc_b64 s[30:31]
18781863
%p = addrspacecast ptr addrspace(8) %buf to ptr addrspace(7)
@@ -2181,14 +2166,14 @@ define <6 x i8> @load_v6i8(ptr addrspace(8) inreg %buf) {
21812166
; GISEL-LABEL: load_v6i8:
21822167
; GISEL: ; %bb.0:
21832168
; GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
2184-
; GISEL-NEXT: buffer_load_dword v0, off, s[16:19], 0
21852169
; GISEL-NEXT: buffer_load_ushort v4, off, s[16:19], 0 offset:4
2170+
; GISEL-NEXT: buffer_load_dword v0, off, s[16:19], 0
21862171
; GISEL-NEXT: s_waitcnt vmcnt(1)
2187-
; GISEL-NEXT: v_lshrrev_b32_e32 v2, 16, v0
2172+
; GISEL-NEXT: v_lshrrev_b32_e32 v5, 8, v4
2173+
; GISEL-NEXT: s_waitcnt vmcnt(0)
21882174
; GISEL-NEXT: v_lshrrev_b32_e32 v1, 8, v0
2175+
; GISEL-NEXT: v_lshrrev_b32_e32 v2, 16, v0
21892176
; GISEL-NEXT: v_lshrrev_b32_e32 v3, 24, v0
2190-
; GISEL-NEXT: s_waitcnt vmcnt(0)
2191-
; GISEL-NEXT: v_lshrrev_b32_e32 v5, 8, v4
21922177
; GISEL-NEXT: s_setpc_b64 s[30:31]
21932178
%p = addrspacecast ptr addrspace(8) %buf to ptr addrspace(7)
21942179
%ret = load <6 x i8>, ptr addrspace(7) %p
@@ -3644,11 +3629,11 @@ define <6 x i8> @volatile_load_v6i8(ptr addrspace(8) inreg %buf) {
36443629
; GISEL-NEXT: buffer_load_dword v0, off, s[16:19], 0 glc
36453630
; GISEL-NEXT: buffer_load_ushort v4, off, s[16:19], 0 offset:4 glc
36463631
; GISEL-NEXT: s_waitcnt vmcnt(1)
3647-
; GISEL-NEXT: v_lshrrev_b32_e32 v2, 16, v0
36483632
; GISEL-NEXT: v_lshrrev_b32_e32 v1, 8, v0
3649-
; GISEL-NEXT: v_lshrrev_b32_e32 v3, 24, v0
36503633
; GISEL-NEXT: s_waitcnt vmcnt(0)
36513634
; GISEL-NEXT: v_lshrrev_b32_e32 v5, 8, v4
3635+
; GISEL-NEXT: v_lshrrev_b32_e32 v2, 16, v0
3636+
; GISEL-NEXT: v_lshrrev_b32_e32 v3, 24, v0
36523637
; GISEL-NEXT: s_setpc_b64 s[30:31]
36533638
%p = addrspacecast ptr addrspace(8) %buf to ptr addrspace(7)
36543639
%ret = load volatile <6 x i8>, ptr addrspace(7) %p

‎llvm/test/CodeGen/AMDGPU/integer-mad-patterns.ll

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -9659,13 +9659,13 @@ define <4 x i16> @multi_use_mul_mad_v2i16_var(<2 x i16> %x, <2 x i16> %y, <2 x i
96599659
; GFX8-GISEL-NEXT: v_lshrrev_b32_e32 v4, 16, v0
96609660
; GFX8-GISEL-NEXT: v_lshrrev_b32_e32 v5, 16, v1
96619661
; GFX8-GISEL-NEXT: v_lshrrev_b32_e32 v6, 16, v2
9662+
; GFX8-GISEL-NEXT: v_lshrrev_b32_e32 v7, 16, v3
96629663
; GFX8-GISEL-NEXT: v_mad_u16 v6, v4, v5, v6
96639664
; GFX8-GISEL-NEXT: v_mad_u16 v2, v0, v1, v2
96649665
; GFX8-GISEL-NEXT: v_lshlrev_b32_e32 v6, 16, v6
9665-
; GFX8-GISEL-NEXT: v_or_b32_e32 v2, v2, v6
9666-
; GFX8-GISEL-NEXT: v_lshrrev_b32_e32 v6, 16, v3
96679666
; GFX8-GISEL-NEXT: v_mad_u16 v0, v0, v1, v3
9668-
; GFX8-GISEL-NEXT: v_mad_u16 v1, v4, v5, v6
9667+
; GFX8-GISEL-NEXT: v_mad_u16 v1, v4, v5, v7
9668+
; GFX8-GISEL-NEXT: v_or_b32_e32 v2, v2, v6
96699669
; GFX8-GISEL-NEXT: v_lshlrev_b32_e32 v1, 16, v1
96709670
; GFX8-GISEL-NEXT: v_or_b32_e32 v1, v0, v1
96719671
; GFX8-GISEL-NEXT: v_mov_b32_e32 v0, v2

‎llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.tbuffer.store.d16.ll

Lines changed: 0 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -187,8 +187,6 @@ define amdgpu_kernel void @tbuffer_store_d16_xyz(<4 x i32> %rsrc, <4 x half> %da
187187
; GFX12-PACKED-GISEL-NEXT: s_load_b64 s[6:7], s[4:5], 0x34
188188
; GFX12-PACKED-GISEL-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
189189
; GFX12-PACKED-GISEL-NEXT: s_wait_kmcnt 0x0
190-
; GFX12-PACKED-GISEL-NEXT: s_pack_lh_b32_b16 s6, s6, s6
191-
; GFX12-PACKED-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
192190
; GFX12-PACKED-GISEL-NEXT: v_mov_b32_e32 v0, s6
193191
; GFX12-PACKED-GISEL-NEXT: v_mov_b32_e32 v1, s7
194192
; GFX12-PACKED-GISEL-NEXT: tbuffer_store_d16_format_xyzw v[0:1], off, s[0:3], null format:[BUF_FMT_10_10_10_2_SNORM]

‎llvm/test/CodeGen/AMDGPU/llvm.amdgcn.struct.tbuffer.store.d16.ll

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -208,10 +208,9 @@ define amdgpu_kernel void @tbuffer_store_d16_xyz(<4 x i32> %rsrc, <4 x half> %da
208208
; GFX12-PACKED-GISEL-NEXT: s_load_b96 s[8:10], s[4:5], 0x10
209209
; GFX12-PACKED-GISEL-NEXT: s_load_b128 s[0:3], s[4:5], 0x0
210210
; GFX12-PACKED-GISEL-NEXT: s_wait_kmcnt 0x0
211-
; GFX12-PACKED-GISEL-NEXT: s_pack_lh_b32_b16 s8, s8, s8
212-
; GFX12-PACKED-GISEL-NEXT: v_mov_b32_e32 v2, s10
213211
; GFX12-PACKED-GISEL-NEXT: v_mov_b32_e32 v0, s8
214212
; GFX12-PACKED-GISEL-NEXT: v_mov_b32_e32 v1, s9
213+
; GFX12-PACKED-GISEL-NEXT: v_mov_b32_e32 v2, s10
215214
; GFX12-PACKED-GISEL-NEXT: tbuffer_store_d16_format_xyzw v[0:1], v2, s[0:3], null format:[BUF_FMT_10_10_10_2_SNORM] idxen
216215
; GFX12-PACKED-GISEL-NEXT: s_endpgm
217216
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