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1 |
| -; RUN: llc < %s -mtriple=arm64-apple-ios7.0.0 | FileCheck %s |
2 |
| -; RUN: llc < %s -mtriple=arm64-apple-ios7.0.0 -O0 -pass-remarks-missed=gisel* -global-isel-abort=2 | FileCheck %s --check-prefixes=GISEL,FALLBACK |
| 1 | +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5 |
| 2 | +; RUN: llc < %s -mtriple=arm64-apple-ios7.0.0 | FileCheck %s --check-prefixes=CHECK,CHECK-SD |
| 3 | +; RUN: llc < %s -mtriple=arm64-apple-ios7.0.0 -global-isel | FileCheck %s --check-prefixes=CHECK,CHECK-GI |
3 | 4 |
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4 | 5 | target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
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5 | 6 |
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6 |
| -; Function Attrs: nounwind readnone |
7 | 7 | declare i32 @llvm.ctlz.i32(i32, i1) #0
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8 | 8 | declare i64 @llvm.ctlz.i64(i64, i1) #1
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9 | 9 |
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10 |
| -; Function Attrs: nounwind ssp |
11 |
| -; FALLBACK-NOT: remark{{.*}}clrsb32 |
12 | 10 | define i32 @clrsb32(i32 %x) #2 {
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| 11 | +; CHECK-LABEL: clrsb32: |
| 12 | +; CHECK: ; %bb.0: ; %entry |
| 13 | +; CHECK-NEXT: cls w0, w0 |
| 14 | +; CHECK-NEXT: ret |
13 | 15 | entry:
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14 | 16 | %shr = ashr i32 %x, 31
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15 | 17 | %xor = xor i32 %shr, %x
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16 | 18 | %mul = shl i32 %xor, 1
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17 | 19 | %add = or i32 %mul, 1
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18 | 20 | %0 = tail call i32 @llvm.ctlz.i32(i32 %add, i1 false)
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19 |
| - |
20 | 21 | ret i32 %0
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21 |
| -; CHECK-LABEL: clrsb32 |
22 |
| -; CHECK: cls [[TEMP:w[0-9]+]], [[TEMP]] |
23 |
| - |
24 |
| -; GISEL-LABEL: clrsb32 |
25 |
| -; GISEL: cls [[TEMP:w[0-9]+]], [[TEMP]] |
26 | 22 | }
|
27 | 23 |
|
28 |
| -; Function Attrs: nounwind ssp |
29 |
| -; FALLBACK-NOT: remark{{.*}}clrsb64 |
30 | 24 | define i64 @clrsb64(i64 %x) #3 {
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| 25 | +; CHECK-LABEL: clrsb64: |
| 26 | +; CHECK: ; %bb.0: ; %entry |
| 27 | +; CHECK-NEXT: cls x0, x0 |
| 28 | +; CHECK-NEXT: ret |
31 | 29 | entry:
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32 | 30 | %shr = ashr i64 %x, 63
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33 | 31 | %xor = xor i64 %shr, %x
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34 | 32 | %mul = shl nsw i64 %xor, 1
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35 | 33 | %add = or i64 %mul, 1
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36 | 34 | %0 = tail call i64 @llvm.ctlz.i64(i64 %add, i1 false)
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37 |
| - |
38 | 35 | ret i64 %0
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39 |
| -; CHECK-LABEL: clrsb64 |
40 |
| -; CHECK: cls [[TEMP:x[0-9]+]], [[TEMP]] |
41 |
| -; GISEL-LABEL: clrsb64 |
42 |
| -; GISEL: cls [[TEMP:x[0-9]+]], [[TEMP]] |
43 | 36 | }
|
44 | 37 |
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45 |
| -; Function Attrs: nounwind ssp |
46 |
| -; FALLBACK-NOT: remark{{.*}}clrsb32_zeroundef |
47 | 38 | define i32 @clrsb32_zeroundef(i32 %x) #2 {
|
| 39 | +; CHECK-LABEL: clrsb32_zeroundef: |
| 40 | +; CHECK: ; %bb.0: ; %entry |
| 41 | +; CHECK-NEXT: cls w0, w0 |
| 42 | +; CHECK-NEXT: ret |
48 | 43 | entry:
|
49 | 44 | %shr = ashr i32 %x, 31
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50 | 45 | %xor = xor i32 %shr, %x
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51 | 46 | %mul = shl i32 %xor, 1
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52 | 47 | %add = or i32 %mul, 1
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53 | 48 | %0 = tail call i32 @llvm.ctlz.i32(i32 %add, i1 true)
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54 |
| - |
55 | 49 | ret i32 %0
|
56 |
| -; CHECK-LABEL: clrsb32_zeroundef |
57 |
| -; CHECK: cls [[TEMP:w[0-9]+]], [[TEMP]] |
58 |
| - |
59 |
| -; GISEL-LABEL: clrsb32_zeroundef |
60 |
| -; GISEL: cls [[TEMP:w[0-9]+]], [[TEMP]] |
61 | 50 | }
|
62 | 51 |
|
63 |
| -; Function Attrs: nounwind ssp |
64 |
| -; FALLBACK-NOT: remark{{.*}}clrsb64 |
65 | 52 | define i64 @clrsb64_zeroundef(i64 %x) #3 {
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| 53 | +; CHECK-LABEL: clrsb64_zeroundef: |
| 54 | +; CHECK: ; %bb.0: ; %entry |
| 55 | +; CHECK-NEXT: cls x0, x0 |
| 56 | +; CHECK-NEXT: ret |
66 | 57 | entry:
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67 | 58 | %shr = ashr i64 %x, 63
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68 | 59 | %xor = xor i64 %shr, %x
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69 | 60 | %mul = shl nsw i64 %xor, 1
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70 | 61 | %add = or i64 %mul, 1
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71 | 62 | %0 = tail call i64 @llvm.ctlz.i64(i64 %add, i1 true)
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72 |
| - |
73 | 63 | ret i64 %0
|
74 |
| -; CHECK-LABEL: clrsb64_zeroundef |
75 |
| -; CHECK: cls [[TEMP:x[0-9]+]], [[TEMP]] |
76 |
| -; GISEL-LABEL: clrsb64_zeroundef |
77 |
| -; GISEL: cls [[TEMP:x[0-9]+]], [[TEMP]] |
78 | 64 | }
|
| 65 | + |
| 66 | +;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line: |
| 67 | +; CHECK-GI: {{.*}} |
| 68 | +; CHECK-SD: {{.*}} |
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