Adjust regpressure test

SamTebbs33 · SamTebbs33 · commit 281a307e2baf · 2025-10-07T10:18:34.000+01:00
diff --git a/llvm/test/Transforms/LoopVectorize/AArch64/maxbandwidth-regpressure.ll b/llvm/test/Transforms/LoopVectorize/AArch64/maxbandwidth-regpressure.ll
@@ -6,8 +6,7 @@ target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
 target triple = "aarch64-none-unknown-elf"
 
 define i32 @dotp(ptr %a, ptr %b) #0 {
-; CHECK-REGS-VP-NOT: LV(REG): Not considering vector loop of width vscale x 16 because it uses too many registers
-; CHECK-REGS-VP: LV: Selecting VF: vscale x 8.
+; CHECK-REGS-VP: LV: Selecting VF: vscale x 16.
 ;
 ; CHECK-NOREGS-VP: LV(REG): Not considering vector loop of width vscale x 8 because it uses too many registers
 ; CHECK-NOREGS-VP: LV(REG): Not considering vector loop of width vscale x 16 because it uses too many registers

Original file line number	Diff line number	Diff line change
`@@ -6,8 +6,7 @@ target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"`
`6`	`6`	`target triple = "aarch64-none-unknown-elf"`
`7`	`7`
`8`	`8`	`define i32 @dotp(ptr %a, ptr %b) #0 {`
`9`		`-; CHECK-REGS-VP-NOT: LV(REG): Not considering vector loop of width vscale x 16 because it uses too many registers`
`10`		`-; CHECK-REGS-VP: LV: Selecting VF: vscale x 8.`
	`9`	`+; CHECK-REGS-VP: LV: Selecting VF: vscale x 16.`
`11`	`10`	`;`
`12`	`11`	`; CHECK-NOREGS-VP: LV(REG): Not considering vector loop of width vscale x 8 because it uses too many registers`
`13`	`12`	`; CHECK-NOREGS-VP: LV(REG): Not considering vector loop of width vscale x 16 because it uses too many registers`