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[AArch64][NFC] Add test for vector sdiv scalarization
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‎llvm/test/CodeGen/AArch64/sdiv-by-const-promoted-ops.ll‎

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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
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; RUN: llc -mtriple=aarch64-none-linux-gnu < %s | FileCheck %s
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define <8 x i16> @sdiv_v8i16_by_7(<8 x i16> %x) {
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; CHECK-LABEL: sdiv_v8i16_by_7:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov w8, #18725 // =0x4925
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; CHECK-NEXT: dup v1.8h, w8
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; CHECK-NEXT: smull2 v2.4s, v0.8h, v1.8h
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; CHECK-NEXT: smull v0.4s, v0.4h, v1.4h
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; CHECK-NEXT: uzp2 v0.8h, v0.8h, v2.8h
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; CHECK-NEXT: sshr v0.8h, v0.8h, #1
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; CHECK-NEXT: usra v0.8h, v0.8h, #15
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; CHECK-NEXT: ret
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%div = sdiv <8 x i16> %x, <i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7>
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ret <8 x i16> %div
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}
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define <16 x i16> @sdiv_v16i16_by_7(<16 x i16> %x) {
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; CHECK-LABEL: sdiv_v16i16_by_7:
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; CHECK: // %bb.0:
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; CHECK-NEXT: smov x11, v0.h[1]
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; CHECK-NEXT: smov x10, v0.h[0]
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; CHECK-NEXT: mov x8, #-56173 // =0xffffffffffff2493
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; CHECK-NEXT: smov x13, v0.h[3]
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; CHECK-NEXT: smov x14, v1.h[1]
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; CHECK-NEXT: movk x8, #37449, lsl #16
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; CHECK-NEXT: smov x16, v1.h[0]
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; CHECK-NEXT: smov w12, v0.h[1]
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; CHECK-NEXT: smov w15, v0.h[0]
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; CHECK-NEXT: smov x18, v1.h[2]
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; CHECK-NEXT: smov w0, v0.h[3]
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; CHECK-NEXT: smov w1, v1.h[1]
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; CHECK-NEXT: smull x11, w11, w8
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; CHECK-NEXT: smov w2, v1.h[0]
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; CHECK-NEXT: smov x9, v0.h[2]
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; CHECK-NEXT: smull x10, w10, w8
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; CHECK-NEXT: smov w17, v0.h[2]
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; CHECK-NEXT: smov w3, v1.h[2]
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; CHECK-NEXT: smull x13, w13, w8
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; CHECK-NEXT: smull x14, w14, w8
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; CHECK-NEXT: add x12, x12, x11, lsr #32
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; CHECK-NEXT: smull x16, w16, w8
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; CHECK-NEXT: add x10, x15, x10, lsr #32
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; CHECK-NEXT: smull x15, w18, w8
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; CHECK-NEXT: add x11, x0, x13, lsr #32
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; CHECK-NEXT: smov x0, v0.h[4]
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; CHECK-NEXT: add x13, x1, x14, lsr #32
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; CHECK-NEXT: asr w18, w10, #2
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; CHECK-NEXT: smull x9, w9, w8
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; CHECK-NEXT: add x14, x2, x16, lsr #32
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; CHECK-NEXT: asr w16, w12, #2
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; CHECK-NEXT: smov x2, v1.h[3]
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; CHECK-NEXT: add w18, w18, w10, lsr #31
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; CHECK-NEXT: add x15, x3, x15, lsr #32
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; CHECK-NEXT: smov w10, v0.h[5]
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; CHECK-NEXT: add w12, w16, w12, lsr #31
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; CHECK-NEXT: asr w16, w14, #2
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; CHECK-NEXT: add x9, x17, x9, lsr #32
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; CHECK-NEXT: fmov s2, w18
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; CHECK-NEXT: smov w17, v0.h[4]
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; CHECK-NEXT: smull x0, w0, w8
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; CHECK-NEXT: add w14, w16, w14, lsr #31
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; CHECK-NEXT: asr w16, w13, #2
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; CHECK-NEXT: asr w1, w9, #2
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; CHECK-NEXT: smov x18, v0.h[5]
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; CHECK-NEXT: fmov s3, w14
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; CHECK-NEXT: mov v2.h[1], w12
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; CHECK-NEXT: add w12, w16, w13, lsr #31
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; CHECK-NEXT: smov w13, v1.h[3]
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; CHECK-NEXT: smov x14, v1.h[4]
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; CHECK-NEXT: smull x16, w2, w8
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; CHECK-NEXT: add w1, w1, w9, lsr #31
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; CHECK-NEXT: add x17, x17, x0, lsr #32
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; CHECK-NEXT: asr w0, w15, #2
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; CHECK-NEXT: mov v3.h[1], w12
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; CHECK-NEXT: smov w12, v1.h[4]
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; CHECK-NEXT: smull x18, w18, w8
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; CHECK-NEXT: mov v2.h[2], w1
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; CHECK-NEXT: asr w1, w11, #2
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; CHECK-NEXT: add w15, w0, w15, lsr #31
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; CHECK-NEXT: add x13, x13, x16, lsr #32
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; CHECK-NEXT: smov x16, v1.h[5]
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; CHECK-NEXT: smull x14, w14, w8
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; CHECK-NEXT: add w11, w1, w11, lsr #31
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; CHECK-NEXT: smov x0, v0.h[6]
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; CHECK-NEXT: add x10, x10, x18, lsr #32
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; CHECK-NEXT: asr w1, w13, #2
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; CHECK-NEXT: mov v3.h[2], w15
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; CHECK-NEXT: smov w15, v1.h[5]
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; CHECK-NEXT: add x12, x12, x14, lsr #32
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; CHECK-NEXT: mov v2.h[3], w11
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; CHECK-NEXT: asr w11, w17, #2
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; CHECK-NEXT: add w13, w1, w13, lsr #31
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; CHECK-NEXT: smull x16, w16, w8
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; CHECK-NEXT: smov x14, v1.h[6]
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; CHECK-NEXT: asr w18, w12, #2
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; CHECK-NEXT: add w11, w11, w17, lsr #31
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; CHECK-NEXT: smov w9, v0.h[6]
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; CHECK-NEXT: mov v3.h[3], w13
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; CHECK-NEXT: smull x17, w0, w8
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; CHECK-NEXT: smov x0, v1.h[7]
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; CHECK-NEXT: add x13, x15, x16, lsr #32
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; CHECK-NEXT: add w12, w18, w12, lsr #31
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; CHECK-NEXT: smov w16, v1.h[6]
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; CHECK-NEXT: mov v2.h[4], w11
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; CHECK-NEXT: smov x11, v0.h[7]
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; CHECK-NEXT: smull x14, w14, w8
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; CHECK-NEXT: asr w15, w10, #2
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; CHECK-NEXT: asr w18, w13, #2
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; CHECK-NEXT: smov w1, v0.h[7]
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; CHECK-NEXT: mov v3.h[4], w12
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; CHECK-NEXT: add x9, x9, x17, lsr #32
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; CHECK-NEXT: add w10, w15, w10, lsr #31
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; CHECK-NEXT: add w12, w18, w13, lsr #31
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; CHECK-NEXT: add x13, x16, x14, lsr #32
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; CHECK-NEXT: smov w14, v1.h[7]
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; CHECK-NEXT: smull x11, w11, w8
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; CHECK-NEXT: smull x8, w0, w8
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; CHECK-NEXT: mov v2.h[5], w10
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; CHECK-NEXT: asr w10, w9, #2
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; CHECK-NEXT: mov v3.h[5], w12
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; CHECK-NEXT: asr w12, w13, #2
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; CHECK-NEXT: add w9, w10, w9, lsr #31
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; CHECK-NEXT: add x10, x1, x11, lsr #32
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; CHECK-NEXT: add w11, w12, w13, lsr #31
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; CHECK-NEXT: add x8, x14, x8, lsr #32
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; CHECK-NEXT: mov v2.h[6], w9
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; CHECK-NEXT: asr w9, w10, #2
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; CHECK-NEXT: mov v3.h[6], w11
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; CHECK-NEXT: asr w11, w8, #2
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; CHECK-NEXT: add w9, w9, w10, lsr #31
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; CHECK-NEXT: add w8, w11, w8, lsr #31
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; CHECK-NEXT: mov v2.h[7], w9
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; CHECK-NEXT: mov v3.h[7], w8
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; CHECK-NEXT: mov v0.16b, v2.16b
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; CHECK-NEXT: mov v1.16b, v3.16b
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; CHECK-NEXT: ret
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%div = sdiv <16 x i16> %x, <i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7>
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ret <16 x i16> %div
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}
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define <8 x i16> @srem_v8i16_by_7(<8 x i16> %x) {
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; CHECK-LABEL: srem_v8i16_by_7:
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; CHECK: // %bb.0:
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; CHECK-NEXT: mov w8, #18725 // =0x4925
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; CHECK-NEXT: dup v1.8h, w8
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; CHECK-NEXT: smull2 v2.4s, v0.8h, v1.8h
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; CHECK-NEXT: smull v1.4s, v0.4h, v1.4h
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; CHECK-NEXT: uzp2 v1.8h, v1.8h, v2.8h
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; CHECK-NEXT: movi v2.8h, #7
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; CHECK-NEXT: sshr v1.8h, v1.8h, #1
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; CHECK-NEXT: usra v1.8h, v1.8h, #15
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; CHECK-NEXT: mls v0.8h, v1.8h, v2.8h
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; CHECK-NEXT: ret
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%rem = srem <8 x i16> %x, <i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7>
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ret <8 x i16> %rem
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}
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define <16 x i16> @srem_v16i16_by_7(<16 x i16> %x) {
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; CHECK-LABEL: srem_v16i16_by_7:
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; CHECK: // %bb.0:
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; CHECK-NEXT: str x19, [sp, #-16]! // 8-byte Folded Spill
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; CHECK-NEXT: .cfi_def_cfa_offset 16
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; CHECK-NEXT: .cfi_offset w19, -16
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; CHECK-NEXT: smov x10, v0.h[0]
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; CHECK-NEXT: smov x9, v0.h[1]
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; CHECK-NEXT: mov x8, #-56173 // =0xffffffffffff2493
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; CHECK-NEXT: smov x15, v0.h[2]
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; CHECK-NEXT: movk x8, #37449, lsl #16
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; CHECK-NEXT: smov x16, v0.h[3]
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; CHECK-NEXT: smov w13, v0.h[0]
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; CHECK-NEXT: smov w12, v0.h[1]
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; CHECK-NEXT: smov x18, v1.h[0]
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; CHECK-NEXT: smov w17, v0.h[2]
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; CHECK-NEXT: smov w14, v0.h[3]
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; CHECK-NEXT: smov w2, v1.h[0]
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; CHECK-NEXT: smull x10, w10, w8
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; CHECK-NEXT: smov x4, v1.h[1]
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; CHECK-NEXT: smov x0, v0.h[4]
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; CHECK-NEXT: smull x9, w9, w8
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; CHECK-NEXT: smov w11, v0.h[4]
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; CHECK-NEXT: smull x15, w15, w8
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; CHECK-NEXT: smull x1, w16, w8
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; CHECK-NEXT: add x10, x13, x10, lsr #32
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; CHECK-NEXT: smov x16, v0.h[5]
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; CHECK-NEXT: add x3, x12, x9, lsr #32
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; CHECK-NEXT: smull x18, w18, w8
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; CHECK-NEXT: smov w9, v0.h[5]
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; CHECK-NEXT: add x15, x17, x15, lsr #32
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; CHECK-NEXT: asr w6, w10, #2
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; CHECK-NEXT: smull x4, w4, w8
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; CHECK-NEXT: asr w5, w3, #2
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; CHECK-NEXT: add x1, x14, x1, lsr #32
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; CHECK-NEXT: smull x0, w0, w8
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; CHECK-NEXT: add x7, x2, x18, lsr #32
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; CHECK-NEXT: asr w19, w15, #2
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; CHECK-NEXT: smov w18, v1.h[1]
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; CHECK-NEXT: add w10, w6, w10, lsr #31
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; CHECK-NEXT: add w3, w5, w3, lsr #31
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; CHECK-NEXT: asr w5, w1, #2
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; CHECK-NEXT: add w6, w19, w15, lsr #31
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; CHECK-NEXT: asr w15, w7, #2
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; CHECK-NEXT: sub w19, w10, w10, lsl #3
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; CHECK-NEXT: add w1, w5, w1, lsr #31
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; CHECK-NEXT: smov x5, v1.h[2]
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; CHECK-NEXT: sub w3, w3, w3, lsl #3
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; CHECK-NEXT: add x4, x18, x4, lsr #32
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; CHECK-NEXT: add w7, w15, w7, lsr #31
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; CHECK-NEXT: add w13, w13, w19
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; CHECK-NEXT: sub w6, w6, w6, lsl #3
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; CHECK-NEXT: sub w1, w1, w1, lsl #3
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; CHECK-NEXT: fmov s2, w13
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; CHECK-NEXT: add w12, w12, w3
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; CHECK-NEXT: add x3, x11, x0, lsr #32
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; CHECK-NEXT: smov w0, v1.h[2]
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; CHECK-NEXT: asr w13, w4, #2
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; CHECK-NEXT: smull x5, w5, w8
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; CHECK-NEXT: sub w7, w7, w7, lsl #3
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; CHECK-NEXT: add w6, w17, w6
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; CHECK-NEXT: smov w17, v1.h[3]
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; CHECK-NEXT: mov v2.h[1], w12
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; CHECK-NEXT: add w13, w13, w4, lsr #31
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; CHECK-NEXT: smov x4, v1.h[3]
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; CHECK-NEXT: add w2, w2, w7
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; CHECK-NEXT: smov x7, v1.h[4]
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; CHECK-NEXT: add w14, w14, w1
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; CHECK-NEXT: add x5, x0, x5, lsr #32
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; CHECK-NEXT: sub w13, w13, w13, lsl #3
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; CHECK-NEXT: fmov s3, w2
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; CHECK-NEXT: smull x2, w16, w8
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; CHECK-NEXT: smov w16, v1.h[4]
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; CHECK-NEXT: asr w12, w3, #2
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; CHECK-NEXT: mov v2.h[2], w6
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; CHECK-NEXT: asr w6, w5, #2
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; CHECK-NEXT: smull x4, w4, w8
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; CHECK-NEXT: add w18, w18, w13
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; CHECK-NEXT: smov x15, v0.h[6]
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; CHECK-NEXT: add w3, w12, w3, lsr #31
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; CHECK-NEXT: add w5, w6, w5, lsr #31
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; CHECK-NEXT: smull x6, w7, w8
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; CHECK-NEXT: mov v3.h[1], w18
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; CHECK-NEXT: add x4, x17, x4, lsr #32
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; CHECK-NEXT: add x1, x9, x2, lsr #32
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; CHECK-NEXT: sub w3, w3, w3, lsl #3
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; CHECK-NEXT: sub w18, w5, w5, lsl #3
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; CHECK-NEXT: smov x5, v1.h[5]
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; CHECK-NEXT: mov v2.h[3], w14
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; CHECK-NEXT: asr w2, w4, #2
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; CHECK-NEXT: smov w10, v0.h[6]
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; CHECK-NEXT: smov x13, v0.h[7]
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; CHECK-NEXT: add w18, w0, w18
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; CHECK-NEXT: add x0, x16, x6, lsr #32
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; CHECK-NEXT: add w11, w11, w3
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; CHECK-NEXT: add w2, w2, w4, lsr #31
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; CHECK-NEXT: smov w4, v1.h[5]
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; CHECK-NEXT: mov v3.h[2], w18
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; CHECK-NEXT: asr w18, w0, #2
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; CHECK-NEXT: smull x5, w5, w8
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; CHECK-NEXT: smov x3, v1.h[7]
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; CHECK-NEXT: sub w14, w2, w2, lsl #3
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; CHECK-NEXT: smov x2, v1.h[6]
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; CHECK-NEXT: smull x15, w15, w8
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; CHECK-NEXT: add w18, w18, w0, lsr #31
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; CHECK-NEXT: asr w6, w1, #2
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; CHECK-NEXT: mov v2.h[4], w11
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; CHECK-NEXT: add w14, w17, w14
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; CHECK-NEXT: add x17, x4, x5, lsr #32
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; CHECK-NEXT: smov w12, v0.h[7]
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; CHECK-NEXT: mov v3.h[3], w14
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; CHECK-NEXT: sub w14, w18, w18, lsl #3
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; CHECK-NEXT: smov w18, v1.h[6]
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; CHECK-NEXT: smull x2, w2, w8
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; CHECK-NEXT: asr w0, w17, #2
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; CHECK-NEXT: add w1, w6, w1, lsr #31
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; CHECK-NEXT: add w11, w16, w14
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; CHECK-NEXT: add x15, x10, x15, lsr #32
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; CHECK-NEXT: smull x13, w13, w8
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; CHECK-NEXT: add w16, w0, w17, lsr #31
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; CHECK-NEXT: smov w17, v1.h[7]
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; CHECK-NEXT: smull x8, w3, w8
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; CHECK-NEXT: mov v3.h[4], w11
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; CHECK-NEXT: add x11, x18, x2, lsr #32
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; CHECK-NEXT: sub w14, w1, w1, lsl #3
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; CHECK-NEXT: asr w0, w15, #2
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; CHECK-NEXT: sub w16, w16, w16, lsl #3
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; CHECK-NEXT: add x13, x12, x13, lsr #32
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; CHECK-NEXT: asr w1, w11, #2
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; CHECK-NEXT: add w9, w9, w14
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; CHECK-NEXT: add w14, w0, w15, lsr #31
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; CHECK-NEXT: add w15, w4, w16
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; CHECK-NEXT: add x8, x17, x8, lsr #32
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; CHECK-NEXT: add w11, w1, w11, lsr #31
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; CHECK-NEXT: mov v2.h[5], w9
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; CHECK-NEXT: mov v3.h[5], w15
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; CHECK-NEXT: sub w9, w14, w14, lsl #3
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; CHECK-NEXT: asr w14, w13, #2
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; CHECK-NEXT: asr w15, w8, #2
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; CHECK-NEXT: sub w11, w11, w11, lsl #3
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; CHECK-NEXT: add w9, w10, w9
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; CHECK-NEXT: add w10, w14, w13, lsr #31
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; CHECK-NEXT: add w8, w15, w8, lsr #31
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; CHECK-NEXT: add w11, w18, w11
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; CHECK-NEXT: mov v2.h[6], w9
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; CHECK-NEXT: mov v3.h[6], w11
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; CHECK-NEXT: sub w9, w10, w10, lsl #3
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; CHECK-NEXT: sub w8, w8, w8, lsl #3
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; CHECK-NEXT: add w9, w12, w9
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; CHECK-NEXT: add w8, w17, w8
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; CHECK-NEXT: mov v2.h[7], w9
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; CHECK-NEXT: mov v3.h[7], w8
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; CHECK-NEXT: mov v0.16b, v2.16b
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; CHECK-NEXT: mov v1.16b, v3.16b
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; CHECK-NEXT: ldr x19, [sp], #16 // 8-byte Folded Reload
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; CHECK-NEXT: ret
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%rem = srem <16 x i16> %x, <i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7, i16 7>
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ret <16 x i16> %rem
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}

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