[AArch64][GlobalISel] Added mir test for saddlp/uaddlp intrinsics

Author: JoshdRod

llvm/test/CodeGen/AArch64/arm64-saddlp1d-uaddlp1d.mir

@@ -0,0 +1,50 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
+# RUN: llc -mtriple=aarch64 -run-pass=regbankselect -verify-machineinstrs %s -o - | FileCheck %s
+
+---
+name:            saddlp1d
+legalized:       true
+regBankSelected: false
+tracksRegLiveness: true
+body:             |
+  bb.1.entry:
+    liveins: $x0
+
+    ; CHECK-LABEL: name: saddlp1d
+    ; CHECK: liveins: $x0
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr(p0) = COPY $x0
+    ; CHECK-NEXT: [[LOAD:%[0-9]+]]:fpr(<2 x s32>) = G_LOAD [[COPY]](p0) :: (load (<2 x s32>))
+    ; CHECK-NEXT: [[SADDLP:%[0-9]+]]:fpr(s64) = G_SADDLP [[LOAD]]
+    ; CHECK-NEXT: $d0 = COPY [[SADDLP]](s64)
+    ; CHECK-NEXT: RET_ReallyLR implicit $d0
+    %0:_(p0) = COPY $x0
+    %1:_(<2 x s32>) = G_LOAD %0(p0) :: (load (<2 x s32>))
+    %2:_(s64) = G_SADDLP %1
+    $d0 = COPY %2(s64)
+    RET_ReallyLR implicit $d0
+...
+---
+name:            uaddlp1d
+legalized:       true
+regBankSelected: false
+failedISel:      false
+tracksRegLiveness: true
+body:             |
+  bb.1.entry:
+    liveins: $x0
+
+    ; CHECK-LABEL: name: uaddlp1d
+    ; CHECK: liveins: $x0
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:gpr(p0) = COPY $x0
+    ; CHECK-NEXT: [[LOAD:%[0-9]+]]:fpr(<2 x s32>) = G_LOAD [[COPY]](p0) :: (load (<2 x s32>))
+    ; CHECK-NEXT: [[UADDLP:%[0-9]+]]:fpr(s64) = G_UADDLP [[LOAD]]
+    ; CHECK-NEXT: $d0 = COPY [[UADDLP]](s64)
+    ; CHECK-NEXT: RET_ReallyLR implicit $d0
+    %0:_(p0) = COPY $x0
+    %1:_(<2 x s32>) = G_LOAD %0(p0) :: (load (<2 x s32>))
+    %2:_(s64) = G_UADDLP %1
+    $d0 = COPY %2(s64)
+    RET_ReallyLR implicit $d0
+...