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1 parent 94c5d8c commit 28fccebCopy full SHA for 28fcceb
mlir/lib/Dialect/Vector/IR/VectorOps.cpp
@@ -2414,8 +2414,8 @@ class FromElementsToShapCast : public OpRewritePattern<FromElementsOp> {
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mlir::OperandRange elements = fromElements.getElements();
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assert(!elements.empty() && "must be at least 1 element");
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-
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Value firstElement = elements.front();
+
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ExtractOp extractOp =
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dyn_cast_if_present<vector::ExtractOp>(firstElement.getDefiningOp());
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if (!extractOp) {
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