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| 1 | +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py |
| 2 | +; RUN: llc -mtriple=armv7a < %s | FileCheck %s --check-prefix=ARM |
| 3 | +; RUN: llc -mtriple=armv6m < %s | FileCheck %s --check-prefix=THUMB |
| 4 | +; RUN: llc -mtriple=armv7m < %s | FileCheck %s --check-prefix=THUMB2 |
| 5 | + |
| 6 | +declare i8 @llvm.smax.i8(i8 %a, i8 %b) readnone |
| 7 | + |
| 8 | +define i8 @smaxi8_zero(i8 %a) { |
| 9 | +; ARM-LABEL: smaxi8_zero: |
| 10 | +; ARM: @ %bb.0: |
| 11 | +; ARM-NEXT: sxtb r0, r0 |
| 12 | +; ARM-NEXT: bic r0, r0, r0, asr #31 |
| 13 | +; ARM-NEXT: bx lr |
| 14 | +; |
| 15 | +; THUMB-LABEL: smaxi8_zero: |
| 16 | +; THUMB: @ %bb.0: |
| 17 | +; THUMB-NEXT: sxtb r0, r0 |
| 18 | +; THUMB-NEXT: asrs r1, r0, #31 |
| 19 | +; THUMB-NEXT: bics r0, r1 |
| 20 | +; THUMB-NEXT: bx lr |
| 21 | +; |
| 22 | +; THUMB2-LABEL: smaxi8_zero: |
| 23 | +; THUMB2: @ %bb.0: |
| 24 | +; THUMB2-NEXT: sxtb r0, r0 |
| 25 | +; THUMB2-NEXT: bic.w r0, r0, r0, asr #31 |
| 26 | +; THUMB2-NEXT: bx lr |
| 27 | + %c = call i8 @llvm.smax.i8(i8 %a, i8 0) |
| 28 | + ret i8 %c |
| 29 | +} |
| 30 | + |
| 31 | +declare i16 @llvm.smax.i16(i16 %a, i16 %b) readnone |
| 32 | + |
| 33 | +define i16 @smaxi16_zero(i16 %a) { |
| 34 | +; ARM-LABEL: smaxi16_zero: |
| 35 | +; ARM: @ %bb.0: |
| 36 | +; ARM-NEXT: sxth r0, r0 |
| 37 | +; ARM-NEXT: bic r0, r0, r0, asr #31 |
| 38 | +; ARM-NEXT: bx lr |
| 39 | +; |
| 40 | +; THUMB-LABEL: smaxi16_zero: |
| 41 | +; THUMB: @ %bb.0: |
| 42 | +; THUMB-NEXT: sxth r0, r0 |
| 43 | +; THUMB-NEXT: asrs r1, r0, #31 |
| 44 | +; THUMB-NEXT: bics r0, r1 |
| 45 | +; THUMB-NEXT: bx lr |
| 46 | +; |
| 47 | +; THUMB2-LABEL: smaxi16_zero: |
| 48 | +; THUMB2: @ %bb.0: |
| 49 | +; THUMB2-NEXT: sxth r0, r0 |
| 50 | +; THUMB2-NEXT: bic.w r0, r0, r0, asr #31 |
| 51 | +; THUMB2-NEXT: bx lr |
| 52 | + %c = call i16 @llvm.smax.i16(i16 %a, i16 0) |
| 53 | + ret i16 %c |
| 54 | +} |
| 55 | + |
| 56 | +declare i32 @llvm.smax.i32(i32 %a, i32 %b) readnone |
| 57 | + |
| 58 | +define i32 @smaxi32_zero(i32 %a) { |
| 59 | +; ARM-LABEL: smaxi32_zero: |
| 60 | +; ARM: @ %bb.0: |
| 61 | +; ARM-NEXT: bic r0, r0, r0, asr #31 |
| 62 | +; ARM-NEXT: bx lr |
| 63 | +; |
| 64 | +; THUMB-LABEL: smaxi32_zero: |
| 65 | +; THUMB: @ %bb.0: |
| 66 | +; THUMB-NEXT: asrs r1, r0, #31 |
| 67 | +; THUMB-NEXT: bics r0, r1 |
| 68 | +; THUMB-NEXT: bx lr |
| 69 | +; |
| 70 | +; THUMB2-LABEL: smaxi32_zero: |
| 71 | +; THUMB2: @ %bb.0: |
| 72 | +; THUMB2-NEXT: bic.w r0, r0, r0, asr #31 |
| 73 | +; THUMB2-NEXT: bx lr |
| 74 | + %c = call i32 @llvm.smax.i32(i32 %a, i32 0) |
| 75 | + ret i32 %c |
| 76 | +} |
| 77 | + |
| 78 | +; SMIN |
| 79 | + |
| 80 | +declare i8 @llvm.smin.i8(i8 %a, i8 %b) readnone |
| 81 | + |
| 82 | +define i8 @smini8_zero(i8 %a) { |
| 83 | +; ARM-LABEL: smini8_zero: |
| 84 | +; ARM: @ %bb.0: |
| 85 | +; ARM-NEXT: sxtb r0, r0 |
| 86 | +; ARM-NEXT: cmp r0, #0 |
| 87 | +; ARM-NEXT: movpl r0, #0 |
| 88 | +; ARM-NEXT: bx lr |
| 89 | +; |
| 90 | +; THUMB-LABEL: smini8_zero: |
| 91 | +; THUMB: @ %bb.0: |
| 92 | +; THUMB-NEXT: sxtb r0, r0 |
| 93 | +; THUMB-NEXT: cmp r0, #0 |
| 94 | +; THUMB-NEXT: bmi .LBB3_2 |
| 95 | +; THUMB-NEXT: @ %bb.1: |
| 96 | +; THUMB-NEXT: movs r0, #0 |
| 97 | +; THUMB-NEXT: .LBB3_2: |
| 98 | +; THUMB-NEXT: bx lr |
| 99 | +; |
| 100 | +; THUMB2-LABEL: smini8_zero: |
| 101 | +; THUMB2: @ %bb.0: |
| 102 | +; THUMB2-NEXT: sxtb r0, r0 |
| 103 | +; THUMB2-NEXT: cmp r0, #0 |
| 104 | +; THUMB2-NEXT: it pl |
| 105 | +; THUMB2-NEXT: movpl r0, #0 |
| 106 | +; THUMB2-NEXT: bx lr |
| 107 | + %c = call i8 @llvm.smin.i8(i8 %a, i8 0) |
| 108 | + ret i8 %c |
| 109 | +} |
| 110 | + |
| 111 | +declare i16 @llvm.smin.i16(i16 %a, i16 %b) readnone |
| 112 | + |
| 113 | +define i16 @smini16_zero(i16 %a) { |
| 114 | +; ARM-LABEL: smini16_zero: |
| 115 | +; ARM: @ %bb.0: |
| 116 | +; ARM-NEXT: sxth r0, r0 |
| 117 | +; ARM-NEXT: cmp r0, #0 |
| 118 | +; ARM-NEXT: movpl r0, #0 |
| 119 | +; ARM-NEXT: bx lr |
| 120 | +; |
| 121 | +; THUMB-LABEL: smini16_zero: |
| 122 | +; THUMB: @ %bb.0: |
| 123 | +; THUMB-NEXT: sxth r0, r0 |
| 124 | +; THUMB-NEXT: cmp r0, #0 |
| 125 | +; THUMB-NEXT: bmi .LBB4_2 |
| 126 | +; THUMB-NEXT: @ %bb.1: |
| 127 | +; THUMB-NEXT: movs r0, #0 |
| 128 | +; THUMB-NEXT: .LBB4_2: |
| 129 | +; THUMB-NEXT: bx lr |
| 130 | +; |
| 131 | +; THUMB2-LABEL: smini16_zero: |
| 132 | +; THUMB2: @ %bb.0: |
| 133 | +; THUMB2-NEXT: sxth r0, r0 |
| 134 | +; THUMB2-NEXT: cmp r0, #0 |
| 135 | +; THUMB2-NEXT: it pl |
| 136 | +; THUMB2-NEXT: movpl r0, #0 |
| 137 | +; THUMB2-NEXT: bx lr |
| 138 | + %c = call i16 @llvm.smin.i16(i16 %a, i16 0) |
| 139 | + ret i16 %c |
| 140 | +} |
| 141 | + |
| 142 | +declare i32 @llvm.smin.i32(i32 %a, i32 %b) readnone |
| 143 | + |
| 144 | +define i32 @smini32_zero(i32 %a) { |
| 145 | +; ARM-LABEL: smini32_zero: |
| 146 | +; ARM: @ %bb.0: |
| 147 | +; ARM-NEXT: cmp r0, #0 |
| 148 | +; ARM-NEXT: movpl r0, #0 |
| 149 | +; ARM-NEXT: bx lr |
| 150 | +; |
| 151 | +; THUMB-LABEL: smini32_zero: |
| 152 | +; THUMB: @ %bb.0: |
| 153 | +; THUMB-NEXT: cmp r0, #0 |
| 154 | +; THUMB-NEXT: bmi .LBB5_2 |
| 155 | +; THUMB-NEXT: @ %bb.1: |
| 156 | +; THUMB-NEXT: movs r0, #0 |
| 157 | +; THUMB-NEXT: .LBB5_2: |
| 158 | +; THUMB-NEXT: bx lr |
| 159 | +; |
| 160 | +; THUMB2-LABEL: smini32_zero: |
| 161 | +; THUMB2: @ %bb.0: |
| 162 | +; THUMB2-NEXT: cmp r0, #0 |
| 163 | +; THUMB2-NEXT: it pl |
| 164 | +; THUMB2-NEXT: movpl r0, #0 |
| 165 | +; THUMB2-NEXT: bx lr |
| 166 | + %c = call i32 @llvm.smin.i32(i32 %a, i32 0) |
| 167 | + ret i32 %c |
| 168 | +} |
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