Eliminate G_TRUNC to S1 SGPR

Author: gandhi56

llvm/lib/Target/AMDGPU/AMDGPURegBankLegalize.cpp

@@ -126,6 +126,7 @@ class AMDGPURegBankLegalizeCombiner {
   bool tryEliminateReadAnyLane(MachineInstr &Copy);
   void tryCombineCopy(MachineInstr &MI);
   void tryCombineS1AnyExt(MachineInstr &MI);
+  void tryCombineTrunc(MachineInstr &MI);
 };
 
 bool AMDGPURegBankLegalizeCombiner::isLaneMask(Register Reg) {
@@ -345,6 +346,25 @@ void AMDGPURegBankLegalizeCombiner::tryCombineS1AnyExt(MachineInstr &MI) {
   llvm_unreachable("missing anyext + trunc combine");
 }
 
+void AMDGPURegBankLegalizeCombiner::tryCombineTrunc(MachineInstr &MI) {
+  if (MI.getOpcode() != AMDGPU::G_TRUNC)
+    return;
+
+  Register Dst = MI.getOperand(0).getReg();
+  Register Src = MI.getOperand(1).getReg();
+  auto *SrcDefMI = MRI.getVRegDef(Src);
+  if (MRI.getType(Dst) != LLT::scalar(1) || !MRI.use_empty(Dst))
+    return;
+
+  if (SrcDefMI && (SrcDefMI->getOpcode() == AMDGPU::G_UADDO ||
+                   SrcDefMI->getOpcode() == AMDGPU::G_USUBO ||
+                   SrcDefMI->getOpcode() == AMDGPU::G_UADDE ||
+                   SrcDefMI->getOpcode() == AMDGPU::G_USUBE)) {
+    MI.eraseFromParent();
+    return;
+  }
+}
+
 // Search through MRI for virtual registers with sgpr register bank and S1 LLT.
 [[maybe_unused]] static Register getAnySgprS1(const MachineRegisterInfo &MRI) {
   const LLT S1 = LLT::scalar(1);
@@ -475,6 +495,10 @@ bool AMDGPURegBankLegalize::runOnMachineFunction(MachineFunction &MF) {
         Combiner.tryCombineCopy(MI);
         continue;
       }
+      if (MI.getOpcode() == AMDGPU::G_TRUNC) {
+        Combiner.tryCombineTrunc(MI);
+        continue;
+      }
       if (MI.getOpcode() == AMDGPU::G_ANYEXT) {
         Combiner.tryCombineS1AnyExt(MI);
         continue;