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[X86] Add missing reg/imm attributes to VRNDSCALES instruction names (#117203)
More canonicalization of the instruction names to make the predictable - more closely matches VRNDSCALEP / VROUND equivalent instructions
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8 files changed

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-109
lines changed

8 files changed

+109
-109
lines changed

‎llvm/lib/Target/X86/X86CompressEVEX.cpp‎

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -154,14 +154,14 @@ static bool performCustomAdjustments(MachineInstr &MI, unsigned NewOpc) {
154154
case X86::VRNDSCALEPDZ256rmi:
155155
case X86::VRNDSCALEPSZ256rri:
156156
case X86::VRNDSCALEPSZ256rmi:
157-
case X86::VRNDSCALESDZr:
158-
case X86::VRNDSCALESDZm:
159-
case X86::VRNDSCALESSZr:
160-
case X86::VRNDSCALESSZm:
161-
case X86::VRNDSCALESDZr_Int:
162-
case X86::VRNDSCALESDZm_Int:
163-
case X86::VRNDSCALESSZr_Int:
164-
case X86::VRNDSCALESSZm_Int:
157+
case X86::VRNDSCALESDZrri:
158+
case X86::VRNDSCALESDZrmi:
159+
case X86::VRNDSCALESSZrri:
160+
case X86::VRNDSCALESSZrmi:
161+
case X86::VRNDSCALESDZrri_Int:
162+
case X86::VRNDSCALESDZrmi_Int:
163+
case X86::VRNDSCALESSZrri_Int:
164+
case X86::VRNDSCALESSZrmi_Int:
165165
const MachineOperand &Imm = MI.getOperand(MI.getNumExplicitOperands() - 1);
166166
int64_t ImmVal = Imm.getImm();
167167
// Ensure that only bits 3:0 of the immediate are used.

‎llvm/lib/Target/X86/X86InstrAVX512.td‎

Lines changed: 7 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -9596,22 +9596,22 @@ defm VSQRT : avx512_sqrt_scalar_all<0x51, "vsqrt", SchedWriteFSqrtSizes>, VEX_LI
95969596
multiclass avx512_rndscale_scalar<bits<8> opc, string OpcodeStr,
95979597
X86FoldableSchedWrite sched, X86VectorVTInfo _> {
95989598
let ExeDomain = _.ExeDomain in {
9599-
defm r_Int : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
9599+
defm rri_Int : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
96009600
(ins _.RC:$src1, _.RC:$src2, i32u8imm:$src3), OpcodeStr,
96019601
"$src3, $src2, $src1", "$src1, $src2, $src3",
96029602
(_.VT (X86RndScales (_.VT _.RC:$src1), (_.VT _.RC:$src2),
96039603
(i32 timm:$src3)))>,
96049604
Sched<[sched]>, SIMD_EXC;
96059605

96069606
let Uses = [MXCSR] in
9607-
defm rb_Int : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
9607+
defm rrib_Int : AVX512_maskable_scalar<opc, MRMSrcReg, _, (outs _.RC:$dst),
96089608
(ins _.RC:$src1, _.RC:$src2, i32u8imm:$src3), OpcodeStr,
96099609
"$src3, {sae}, $src2, $src1", "$src1, $src2, {sae}, $src3",
96109610
(_.VT (X86RndScalesSAE (_.VT _.RC:$src1), (_.VT _.RC:$src2),
96119611
(i32 timm:$src3)))>, EVEX_B,
96129612
Sched<[sched]>;
96139613

9614-
defm m_Int : AVX512_maskable_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst),
9614+
defm rmi_Int : AVX512_maskable_scalar<opc, MRMSrcMem, _, (outs _.RC:$dst),
96159615
(ins _.RC:$src1, _.IntScalarMemOp:$src2, i32u8imm:$src3),
96169616
OpcodeStr,
96179617
"$src3, $src2, $src1", "$src1, $src2, $src3",
@@ -9620,13 +9620,13 @@ multiclass avx512_rndscale_scalar<bits<8> opc, string OpcodeStr,
96209620
Sched<[sched.Folded, sched.ReadAfterFold]>, SIMD_EXC;
96219621

96229622
let isCodeGenOnly = 1, hasSideEffects = 0, Predicates = [HasAVX512] in {
9623-
def r : I<opc, MRMSrcReg, (outs _.FRC:$dst),
9623+
def rri : I<opc, MRMSrcReg, (outs _.FRC:$dst),
96249624
(ins _.FRC:$src1, _.FRC:$src2, i32u8imm:$src3),
96259625
OpcodeStr#"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
96269626
[]>, Sched<[sched]>, SIMD_EXC;
96279627

96289628
let mayLoad = 1 in
9629-
def m : I<opc, MRMSrcMem, (outs _.FRC:$dst),
9629+
def rmi : I<opc, MRMSrcMem, (outs _.FRC:$dst),
96309630
(ins _.FRC:$src1, _.ScalarMemOp:$src2, i32u8imm:$src3),
96319631
OpcodeStr#"\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}",
96329632
[]>, Sched<[sched.Folded, sched.ReadAfterFold]>, SIMD_EXC;
@@ -9635,13 +9635,13 @@ multiclass avx512_rndscale_scalar<bits<8> opc, string OpcodeStr,
96359635

96369636
let Predicates = [HasAVX512] in {
96379637
def : Pat<(X86any_VRndScale _.FRC:$src1, timm:$src2),
9638-
(_.EltVT (!cast<Instruction>(NAME#r) (_.EltVT (IMPLICIT_DEF)),
9638+
(_.EltVT (!cast<Instruction>(NAME#rri) (_.EltVT (IMPLICIT_DEF)),
96399639
_.FRC:$src1, timm:$src2))>;
96409640
}
96419641

96429642
let Predicates = [HasAVX512, OptForSize] in {
96439643
def : Pat<(X86any_VRndScale (_.ScalarLdFrag addr:$src1), timm:$src2),
9644-
(_.EltVT (!cast<Instruction>(NAME#m) (_.EltVT (IMPLICIT_DEF)),
9644+
(_.EltVT (!cast<Instruction>(NAME#rmi) (_.EltVT (IMPLICIT_DEF)),
96459645
addr:$src1, timm:$src2))>;
96469646
}
96479647
}

‎llvm/lib/Target/X86/X86InstrInfo.cpp‎

Lines changed: 21 additions & 21 deletions
Original file line numberDiff line numberDiff line change
@@ -6971,16 +6971,16 @@ static bool hasUndefRegUpdate(unsigned Opcode, unsigned OpNum,
69716971
case X86::VGETMANTSSZrri:
69726972
case X86::VGETMANTSSZrrib:
69736973
case X86::VGETMANTSSZrmi:
6974-
case X86::VRNDSCALESDZr:
6975-
case X86::VRNDSCALESDZr_Int:
6976-
case X86::VRNDSCALESDZrb_Int:
6977-
case X86::VRNDSCALESDZm:
6978-
case X86::VRNDSCALESDZm_Int:
6979-
case X86::VRNDSCALESSZr:
6980-
case X86::VRNDSCALESSZr_Int:
6981-
case X86::VRNDSCALESSZrb_Int:
6982-
case X86::VRNDSCALESSZm:
6983-
case X86::VRNDSCALESSZm_Int:
6974+
case X86::VRNDSCALESDZrri:
6975+
case X86::VRNDSCALESDZrri_Int:
6976+
case X86::VRNDSCALESDZrrib_Int:
6977+
case X86::VRNDSCALESDZrmi:
6978+
case X86::VRNDSCALESDZrmi_Int:
6979+
case X86::VRNDSCALESSZrri:
6980+
case X86::VRNDSCALESSZrri_Int:
6981+
case X86::VRNDSCALESSZrrib_Int:
6982+
case X86::VRNDSCALESSZrmi:
6983+
case X86::VRNDSCALESSZrmi_Int:
69846984
case X86::VRCP14SDZrr:
69856985
case X86::VRCP14SDZrm:
69866986
case X86::VRCP14SSZrr:
@@ -6998,11 +6998,11 @@ static bool hasUndefRegUpdate(unsigned Opcode, unsigned OpNum,
69986998
case X86::VGETMANTSHZrri:
69996999
case X86::VGETMANTSHZrrib:
70007000
case X86::VGETMANTSHZrmi:
7001-
case X86::VRNDSCALESHZr:
7002-
case X86::VRNDSCALESHZr_Int:
7003-
case X86::VRNDSCALESHZrb_Int:
7004-
case X86::VRNDSCALESHZm:
7005-
case X86::VRNDSCALESHZm_Int:
7001+
case X86::VRNDSCALESHZrri:
7002+
case X86::VRNDSCALESHZrri_Int:
7003+
case X86::VRNDSCALESHZrrib_Int:
7004+
case X86::VRNDSCALESHZrmi:
7005+
case X86::VRNDSCALESHZrmi_Int:
70067006
case X86::VSQRTSHZr:
70077007
case X86::VSQRTSHZr_Int:
70087008
case X86::VSQRTSHZrb_Int:
@@ -7790,9 +7790,9 @@ static bool isNonFoldablePartialRegisterLoad(const MachineInstr &LoadMI,
77907790
case X86::VREDUCESSZrri:
77917791
case X86::VREDUCESSZrrik:
77927792
case X86::VREDUCESSZrrikz:
7793-
case X86::VRNDSCALESSZr_Int:
7794-
case X86::VRNDSCALESSZr_Intk:
7795-
case X86::VRNDSCALESSZr_Intkz:
7793+
case X86::VRNDSCALESSZrri_Int:
7794+
case X86::VRNDSCALESSZrri_Intk:
7795+
case X86::VRNDSCALESSZrri_Intkz:
77967796
case X86::VRSQRT14SSZrr:
77977797
case X86::VRSQRT14SSZrrk:
77987798
case X86::VRSQRT14SSZrrkz:
@@ -7959,9 +7959,9 @@ static bool isNonFoldablePartialRegisterLoad(const MachineInstr &LoadMI,
79597959
case X86::VREDUCESDZrri:
79607960
case X86::VREDUCESDZrrik:
79617961
case X86::VREDUCESDZrrikz:
7962-
case X86::VRNDSCALESDZr_Int:
7963-
case X86::VRNDSCALESDZr_Intk:
7964-
case X86::VRNDSCALESDZr_Intkz:
7962+
case X86::VRNDSCALESDZrri_Int:
7963+
case X86::VRNDSCALESDZrri_Intk:
7964+
case X86::VRNDSCALESDZrri_Intkz:
79657965
case X86::VRSQRT14SDZrr:
79667966
case X86::VRSQRT14SDZrrk:
79677967
case X86::VRSQRT14SDZrrkz:

‎llvm/lib/Target/X86/X86SchedSapphireRapids.td‎

Lines changed: 9 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -2300,8 +2300,8 @@ def : InstRW<[SPRWriteResGroup218, ReadAfterVecXLd], (instregex "^(V?)ROUNDS(D|S
23002300
"^VRNDSCALEP(D|S)Z128rm(bi|ik)$",
23012301
"^VRNDSCALEP(D|S)Z128rmbik(z?)$",
23022302
"^VRNDSCALEP(D|S)Z128rmi((kz)?)$",
2303-
"^VRNDSCALES(D|S)Zm$",
2304-
"^VRNDSCALES(D|S)Zm_Int((k|kz)?)$")>;
2303+
"^VRNDSCALES(D|S)Zrmi$",
2304+
"^VRNDSCALES(D|S)Zrmi_Int((k|kz)?)$")>;
23052305

23062306
def SPRWriteResGroup219 : SchedWriteRes<[SPRPort00_01]> {
23072307
let ReleaseAtCycles = [2];
@@ -2312,8 +2312,8 @@ def : InstRW<[SPRWriteResGroup219], (instregex "^(V?)ROUND(PD|SS)ri$",
23122312
"^(V?)ROUND(PS|SD)ri$",
23132313
"^(V?)ROUNDS(D|S)ri_Int$",
23142314
"^VRNDSCALEP(D|S)Z(128|256)rri((k|kz)?)$",
2315-
"^VRNDSCALES(D|S)Zr$",
2316-
"^VRNDSCALES(D|S)Zr(b?)_Int((k|kz)?)$",
2315+
"^VRNDSCALES(D|S)Zrri$",
2316+
"^VRNDSCALES(D|S)Zrri(b?)_Int((k|kz)?)$",
23172317
"^VROUNDP(D|S)Yri$")>;
23182318

23192319
def SPRWriteResGroup220 : SchedWriteRes<[SPRPort00_06]> {
@@ -3747,7 +3747,7 @@ def : InstRW<[SPRWriteResGroup390, ReadAfterVecXLd], (instregex "^VF(C?)MADDCSHZ
37473747
"^VF(C?)MULCPHZ128rm(b?)$",
37483748
"^VF(C?)MULCSHZrm$",
37493749
"^VRNDSCALEPHZ128rm(b?)i$",
3750-
"^VRNDSCALESHZm((_Int)?)$",
3750+
"^VRNDSCALESHZrmi((_Int)?)$",
37513751
"^VSCALEFPHZ128rm(b?)$")>;
37523752
def : InstRW<[SPRWriteResGroup390, ReadAfterVecYLd], (instregex "^VF(C?)MULCPHZ256rm(b?)$",
37533753
"^VRNDSCALEP(D|H|S)Z256rm(b?)i$",
@@ -3779,9 +3779,9 @@ def : InstRW<[SPRWriteResGroup392], (instregex "^VF(C?)MADDCPHZ(128|256)r$",
37793779
"^VF(C?)MULCPHZ(128|256)rr$",
37803780
"^VF(C?)MULCSHZrr(b?)$",
37813781
"^VRNDSCALEPHZ(128|256)rri$",
3782-
"^VRNDSCALESHZr(b?)_Int$",
3782+
"^VRNDSCALESHZrri(b?)_Int$",
37833783
"^VSCALEFPHZ(128|256)rr$")>;
3784-
def : InstRW<[SPRWriteResGroup392], (instrs VRNDSCALESHZr,
3784+
def : InstRW<[SPRWriteResGroup392], (instrs VRNDSCALESHZrri,
37853785
VSCALEFSHZrr,
37863786
VSCALEFSHZrrb_Int)>;
37873787

@@ -4884,7 +4884,7 @@ def SPRWriteResGroup534 : SchedWriteRes<[SPRPort00_01, SPRPort02_03_11]> {
48844884
let NumMicroOps = 3;
48854885
}
48864886
def : InstRW<[SPRWriteResGroup534, ReadAfterVecXLd], (instregex "^VRNDSCALEPHZ128rm(b?)ik(z?)$",
4887-
"^VRNDSCALESHZm_Intk(z?)$",
4887+
"^VRNDSCALESHZrmi_Intk(z?)$",
48884888
"^VSCALEFPHZ128rm(bk|kz)$",
48894889
"^VSCALEFPHZ128rm(k|bkz)$")>;
48904890
def : InstRW<[SPRWriteResGroup534, ReadAfterVecYLd], (instregex "^VRNDSCALEPHZ256rm(b?)ik(z?)$",
@@ -4898,7 +4898,7 @@ def SPRWriteResGroup535 : SchedWriteRes<[SPRPort00_01]> {
48984898
let NumMicroOps = 2;
48994899
}
49004900
def : InstRW<[SPRWriteResGroup535], (instregex "^VRNDSCALEPHZ(128|256)rrik(z?)$",
4901-
"^VRNDSCALESHZr(b?)_Intk(z?)$",
4901+
"^VRNDSCALESHZrri(b?)_Intk(z?)$",
49024902
"^VSCALEFPHZ(128|256)rrk(z?)$",
49034903
"^VSCALEFSHZrrb_Intk(z?)$",
49044904
"^VSCALEFSHZrrk(z?)$")>;

‎llvm/test/CodeGen/X86/evex-to-vex-compress.mir‎

Lines changed: 40 additions & 40 deletions
Original file line numberDiff line numberDiff line change
@@ -2309,21 +2309,21 @@ body: |
23092309
; CHECK: $xmm0 = VINSERTPSrri $xmm0, $xmm0, 1
23102310
$xmm0 = VINSERTPSZrri $xmm0, $xmm0, 1
23112311
; CHECK: $xmm0 = VROUNDSDmi $xmm0, $rip, 1, $noreg, 0, $noreg, 15, implicit $mxcsr
2312-
$xmm0 = VRNDSCALESDZm $xmm0, $rip, 1, $noreg, 0, $noreg, 15, implicit $mxcsr
2312+
$xmm0 = VRNDSCALESDZrmi $xmm0, $rip, 1, $noreg, 0, $noreg, 15, implicit $mxcsr
23132313
; CHECK: $xmm0 = VROUNDSDri $xmm0, $xmm1, 15, implicit $mxcsr
2314-
$xmm0 = VRNDSCALESDZr $xmm0, $xmm1, 15, implicit $mxcsr
2314+
$xmm0 = VRNDSCALESDZrri $xmm0, $xmm1, 15, implicit $mxcsr
23152315
; CHECK: $xmm0 = VROUNDSSmi $xmm0, $rip, 1, $noreg, 0, $noreg, 15, implicit $mxcsr
2316-
$xmm0 = VRNDSCALESSZm $xmm0, $rip, 1, $noreg, 0, $noreg, 15, implicit $mxcsr
2316+
$xmm0 = VRNDSCALESSZrmi $xmm0, $rip, 1, $noreg, 0, $noreg, 15, implicit $mxcsr
23172317
; CHECK: $xmm0 = VROUNDSSri $xmm0, $xmm1, 15, implicit $mxcsr
2318-
$xmm0 = VRNDSCALESSZr $xmm0, $xmm1, 15, implicit $mxcsr
2318+
$xmm0 = VRNDSCALESSZrri $xmm0, $xmm1, 15, implicit $mxcsr
23192319
; CHECK: $xmm0 = VROUNDSDmi_Int $xmm0, $rip, 1, $noreg, 0, $noreg, 15, implicit $mxcsr
2320-
$xmm0 = VRNDSCALESDZm_Int $xmm0, $rip, 1, $noreg, 0, $noreg, 15, implicit $mxcsr
2320+
$xmm0 = VRNDSCALESDZrmi_Int $xmm0, $rip, 1, $noreg, 0, $noreg, 15, implicit $mxcsr
23212321
; CHECK: $xmm0 = VROUNDSDri_Int $xmm0, $xmm1, 15, implicit $mxcsr
2322-
$xmm0 = VRNDSCALESDZr_Int $xmm0, $xmm1, 15, implicit $mxcsr
2322+
$xmm0 = VRNDSCALESDZrri_Int $xmm0, $xmm1, 15, implicit $mxcsr
23232323
; CHECK: $xmm0 = VROUNDSSmi_Int $xmm0, $rip, 1, $noreg, 0, $noreg, 15, implicit $mxcsr
2324-
$xmm0 = VRNDSCALESSZm_Int $xmm0, $rip, 1, $noreg, 0, $noreg, 15, implicit $mxcsr
2324+
$xmm0 = VRNDSCALESSZrmi_Int $xmm0, $rip, 1, $noreg, 0, $noreg, 15, implicit $mxcsr
23252325
; CHECK: $xmm0 = VROUNDSSri_Int $xmm0, $xmm1, 15, implicit $mxcsr
2326-
$xmm0 = VRNDSCALESSZr_Int $xmm0, $xmm1, 15, implicit $mxcsr
2326+
$xmm0 = VRNDSCALESSZrri_Int $xmm0, $xmm1, 15, implicit $mxcsr
23272327
23282328
RET64
23292329
...
@@ -4636,38 +4636,38 @@ body: |
46364636
VUCOMISSZrm $xmm16, $rdi, 1, $noreg, 0, $noreg, implicit-def $eflags, implicit $mxcsr
46374637
; CHECK: VUCOMISSZrr $xmm16, $xmm1, implicit-def $eflags, implicit $mxcsr
46384638
VUCOMISSZrr $xmm16, $xmm1, implicit-def $eflags, implicit $mxcsr
4639-
; CHECK: $xmm16 = VRNDSCALESDZm $xmm16, $rip, 1, $noreg, 0, $noreg, 15, implicit $mxcsr
4640-
$xmm16 = VRNDSCALESDZm $xmm16, $rip, 1, $noreg, 0, $noreg, 15, implicit $mxcsr
4641-
; CHECK: $xmm16 = VRNDSCALESDZr $xmm16, $xmm1, 15, implicit $mxcsr
4642-
$xmm16 = VRNDSCALESDZr $xmm16, $xmm1, 15, implicit $mxcsr
4643-
; CHECK: $xmm16 = VRNDSCALESSZm $xmm16, $rip, 1, $noreg, 0, $noreg, 15, implicit $mxcsr
4644-
$xmm16 = VRNDSCALESSZm $xmm16, $rip, 1, $noreg, 0, $noreg, 15, implicit $mxcsr
4645-
; CHECK: $xmm16 = VRNDSCALESSZr $xmm16, $xmm1, 15, implicit $mxcsr
4646-
$xmm16 = VRNDSCALESSZr $xmm16, $xmm1, 15, implicit $mxcsr
4647-
; CHECK: $xmm16 = VRNDSCALESDZm_Int $xmm16, $rip, 1, $noreg, 0, $noreg, 15, implicit $mxcsr
4648-
$xmm16 = VRNDSCALESDZm_Int $xmm16, $rip, 1, $noreg, 0, $noreg, 15, implicit $mxcsr
4649-
; CHECK: $xmm16 = VRNDSCALESDZr_Int $xmm16, $xmm1, 15, implicit $mxcsr
4650-
$xmm16 = VRNDSCALESDZr_Int $xmm16, $xmm1, 15, implicit $mxcsr
4651-
; CHECK: $xmm16 = VRNDSCALESSZm_Int $xmm16, $rip, 1, $noreg, 0, $noreg, 15, implicit $mxcsr
4652-
$xmm16 = VRNDSCALESSZm_Int $xmm16, $rip, 1, $noreg, 0, $noreg, 15, implicit $mxcsr
4653-
; CHECK: $xmm16 = VRNDSCALESSZr_Int $xmm16, $xmm1, 15, implicit $mxcsr
4654-
$xmm16 = VRNDSCALESSZr_Int $xmm16, $xmm1, 15, implicit $mxcsr
4655-
; CHECK: $xmm0 = VRNDSCALESDZm $xmm0, $rip, 1, $noreg, 0, $noreg, 31, implicit $mxcsr
4656-
$xmm0 = VRNDSCALESDZm $xmm0, $rip, 1, $noreg, 0, $noreg, 31, implicit $mxcsr
4657-
; CHECK: $xmm0 = VRNDSCALESDZr $xmm0, $xmm1, 31, implicit $mxcsr
4658-
$xmm0 = VRNDSCALESDZr $xmm0, $xmm1, 31, implicit $mxcsr
4659-
; CHECK: $xmm0 = VRNDSCALESSZm $xmm0, $rip, 1, $noreg, 0, $noreg, 31, implicit $mxcsr
4660-
$xmm0 = VRNDSCALESSZm $xmm0, $rip, 1, $noreg, 0, $noreg, 31, implicit $mxcsr
4661-
; CHECK: $xmm0 = VRNDSCALESSZr $xmm0, $xmm1, 31, implicit $mxcsr
4662-
$xmm0 = VRNDSCALESSZr $xmm0, $xmm1, 31, implicit $mxcsr
4663-
; CHECK: $xmm0 = VRNDSCALESDZm_Int $xmm0, $rip, 1, $noreg, 0, $noreg, 31, implicit $mxcsr
4664-
$xmm0 = VRNDSCALESDZm_Int $xmm0, $rip, 1, $noreg, 0, $noreg, 31, implicit $mxcsr
4665-
; CHECK: $xmm0 = VRNDSCALESDZr_Int $xmm0, $xmm1, 31, implicit $mxcsr
4666-
$xmm0 = VRNDSCALESDZr_Int $xmm0, $xmm1, 31, implicit $mxcsr
4667-
; CHECK: $xmm0 = VRNDSCALESSZm_Int $xmm0, $rip, 1, $noreg, 0, $noreg, 31, implicit $mxcsr
4668-
$xmm0 = VRNDSCALESSZm_Int $xmm0, $rip, 1, $noreg, 0, $noreg, 31, implicit $mxcsr
4669-
; CHECK: $xmm0 = VRNDSCALESSZr_Int $xmm0, $xmm1, 31, implicit $mxcsr
4670-
$xmm0 = VRNDSCALESSZr_Int $xmm0, $xmm1, 31, implicit $mxcsr
4639+
; CHECK: $xmm16 = VRNDSCALESDZrmi $xmm16, $rip, 1, $noreg, 0, $noreg, 15, implicit $mxcsr
4640+
$xmm16 = VRNDSCALESDZrmi $xmm16, $rip, 1, $noreg, 0, $noreg, 15, implicit $mxcsr
4641+
; CHECK: $xmm16 = VRNDSCALESDZrri $xmm16, $xmm1, 15, implicit $mxcsr
4642+
$xmm16 = VRNDSCALESDZrri $xmm16, $xmm1, 15, implicit $mxcsr
4643+
; CHECK: $xmm16 = VRNDSCALESSZrmi $xmm16, $rip, 1, $noreg, 0, $noreg, 15, implicit $mxcsr
4644+
$xmm16 = VRNDSCALESSZrmi $xmm16, $rip, 1, $noreg, 0, $noreg, 15, implicit $mxcsr
4645+
; CHECK: $xmm16 = VRNDSCALESSZrri $xmm16, $xmm1, 15, implicit $mxcsr
4646+
$xmm16 = VRNDSCALESSZrri $xmm16, $xmm1, 15, implicit $mxcsr
4647+
; CHECK: $xmm16 = VRNDSCALESDZrmi_Int $xmm16, $rip, 1, $noreg, 0, $noreg, 15, implicit $mxcsr
4648+
$xmm16 = VRNDSCALESDZrmi_Int $xmm16, $rip, 1, $noreg, 0, $noreg, 15, implicit $mxcsr
4649+
; CHECK: $xmm16 = VRNDSCALESDZrri_Int $xmm16, $xmm1, 15, implicit $mxcsr
4650+
$xmm16 = VRNDSCALESDZrri_Int $xmm16, $xmm1, 15, implicit $mxcsr
4651+
; CHECK: $xmm16 = VRNDSCALESSZrmi_Int $xmm16, $rip, 1, $noreg, 0, $noreg, 15, implicit $mxcsr
4652+
$xmm16 = VRNDSCALESSZrmi_Int $xmm16, $rip, 1, $noreg, 0, $noreg, 15, implicit $mxcsr
4653+
; CHECK: $xmm16 = VRNDSCALESSZrri_Int $xmm16, $xmm1, 15, implicit $mxcsr
4654+
$xmm16 = VRNDSCALESSZrri_Int $xmm16, $xmm1, 15, implicit $mxcsr
4655+
; CHECK: $xmm0 = VRNDSCALESDZrmi $xmm0, $rip, 1, $noreg, 0, $noreg, 31, implicit $mxcsr
4656+
$xmm0 = VRNDSCALESDZrmi $xmm0, $rip, 1, $noreg, 0, $noreg, 31, implicit $mxcsr
4657+
; CHECK: $xmm0 = VRNDSCALESDZrri $xmm0, $xmm1, 31, implicit $mxcsr
4658+
$xmm0 = VRNDSCALESDZrri $xmm0, $xmm1, 31, implicit $mxcsr
4659+
; CHECK: $xmm0 = VRNDSCALESSZrmi $xmm0, $rip, 1, $noreg, 0, $noreg, 31, implicit $mxcsr
4660+
$xmm0 = VRNDSCALESSZrmi $xmm0, $rip, 1, $noreg, 0, $noreg, 31, implicit $mxcsr
4661+
; CHECK: $xmm0 = VRNDSCALESSZrri $xmm0, $xmm1, 31, implicit $mxcsr
4662+
$xmm0 = VRNDSCALESSZrri $xmm0, $xmm1, 31, implicit $mxcsr
4663+
; CHECK: $xmm0 = VRNDSCALESDZrmi_Int $xmm0, $rip, 1, $noreg, 0, $noreg, 31, implicit $mxcsr
4664+
$xmm0 = VRNDSCALESDZrmi_Int $xmm0, $rip, 1, $noreg, 0, $noreg, 31, implicit $mxcsr
4665+
; CHECK: $xmm0 = VRNDSCALESDZrri_Int $xmm0, $xmm1, 31, implicit $mxcsr
4666+
$xmm0 = VRNDSCALESDZrri_Int $xmm0, $xmm1, 31, implicit $mxcsr
4667+
; CHECK: $xmm0 = VRNDSCALESSZrmi_Int $xmm0, $rip, 1, $noreg, 0, $noreg, 31, implicit $mxcsr
4668+
$xmm0 = VRNDSCALESSZrmi_Int $xmm0, $rip, 1, $noreg, 0, $noreg, 31, implicit $mxcsr
4669+
; CHECK: $xmm0 = VRNDSCALESSZrri_Int $xmm0, $xmm1, 31, implicit $mxcsr
4670+
$xmm0 = VRNDSCALESSZrri_Int $xmm0, $xmm1, 31, implicit $mxcsr
46714671
46724672
RET64
46734673
...

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