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-42
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3 files changed

+29
-42
lines changed

‎llvm/lib/Transforms/Vectorize/VectorCombine.cpp‎

Lines changed: 1 addition & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -987,7 +987,7 @@ static Constant *getLosslessInvCast(Constant *C, Type *InvCastTo,
987987
// bitop(castop(x), C) ->
988988
// bitop(castop(x), castop(InvC)) ->
989989
// castop(bitop(x, InvC))
990-
// Supports: bitcast, trunc, sext, zext
990+
// Supports: bitcast
991991
bool VectorCombine::foldBitOpOfCastConstant(Instruction &I) {
992992
Instruction *LHS;
993993
Constant *C;
@@ -1006,9 +1006,6 @@ bool VectorCombine::foldBitOpOfCastConstant(Instruction &I) {
10061006
// Only handle supported cast operations
10071007
switch (CastOpcode) {
10081008
case Instruction::BitCast:
1009-
case Instruction::Trunc:
1010-
case Instruction::SExt:
1011-
case Instruction::ZExt:
10121009
break;
10131010
default:
10141011
return false;
@@ -1074,16 +1071,6 @@ bool VectorCombine::foldBitOpOfCastConstant(Instruction &I) {
10741071
// Create the cast operation directly to ensure we get a new instruction
10751072
Instruction *NewCast = CastInst::Create(CastOpcode, NewOp, I.getType());
10761073

1077-
// Preserve cast instruction flags
1078-
if (RHSFlags.NNeg)
1079-
NewCast->setNonNeg();
1080-
if (RHSFlags.NSW)
1081-
NewCast->setHasNoSignedWrap();
1082-
if (RHSFlags.NUW)
1083-
NewCast->setHasNoUnsignedWrap();
1084-
1085-
NewCast->andIRFlags(LHSCast);
1086-
10871074
// Insert the new instruction
10881075
Value *Result = Builder.Insert(NewCast);
10891076

‎llvm/test/Transforms/VectorCombine/AArch64/shrink-types.ll‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -45,11 +45,11 @@ define i32 @multiuse(<16 x i32> %u, <16 x i32> %v, ptr %b) {
4545
; CHECK-NEXT: [[U_MASKED:%.*]] = and <16 x i32> [[U:%.*]], splat (i32 255)
4646
; CHECK-NEXT: [[V_MASKED:%.*]] = and <16 x i32> [[V:%.*]], splat (i32 255)
4747
; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <16 x i8>, ptr [[B:%.*]], align 1
48+
; CHECK-NEXT: [[TMP0:%.*]] = zext <16 x i8> [[WIDE_LOAD]] to <16 x i32>
4849
; CHECK-NEXT: [[TMP6:%.*]] = lshr <16 x i8> [[WIDE_LOAD]], splat (i8 4)
4950
; CHECK-NEXT: [[TMP7:%.*]] = zext <16 x i8> [[TMP6]] to <16 x i32>
5051
; CHECK-NEXT: [[TMP3:%.*]] = or <16 x i32> [[TMP7]], [[V_MASKED]]
51-
; CHECK-NEXT: [[DOTINNER:%.*]] = and <16 x i8> [[WIDE_LOAD]], splat (i8 15)
52-
; CHECK-NEXT: [[TMP4:%.*]] = zext <16 x i8> [[DOTINNER]] to <16 x i32>
52+
; CHECK-NEXT: [[TMP4:%.*]] = and <16 x i32> [[TMP0]], splat (i32 15)
5353
; CHECK-NEXT: [[TMP5:%.*]] = or <16 x i32> [[TMP4]], [[U_MASKED]]
5454
; CHECK-NEXT: [[TMP8:%.*]] = add nuw nsw <16 x i32> [[TMP3]], [[TMP5]]
5555
; CHECK-NEXT: [[TMP9:%.*]] = call i32 @llvm.vector.reduce.add.v16i32(<16 x i32> [[TMP8]])

‎llvm/test/Transforms/VectorCombine/X86/bitop-of-castops.ll‎

Lines changed: 26 additions & 26 deletions
Original file line numberDiff line numberDiff line change
@@ -287,9 +287,9 @@ define <2 x i32> @or_bitcast_v4i16_to_v2i32_constant_commuted(<4 x i16> %a) {
287287
; Test bitwise operations with truncate and one constant
288288
define <4 x i16> @or_trunc_v4i32_to_v4i16_constant(<4 x i32> %a) {
289289
; CHECK-LABEL: @or_trunc_v4i32_to_v4i16_constant(
290-
; CHECK-NEXT: [[A:%.*]] = or <4 x i32> [[A1:%.*]], <i32 1, i32 2, i32 3, i32 4>
291-
; CHECK-NEXT: [[T1:%.*]] = trunc <4 x i32> [[A]] to <4 x i16>
292-
; CHECK-NEXT: ret <4 x i16> [[T1]]
290+
; CHECK-NEXT: [[T1:%.*]] = trunc <4 x i32> [[A:%.*]] to <4 x i16>
291+
; CHECK-NEXT: [[OR:%.*]] = or <4 x i16> [[T1]], <i16 1, i16 2, i16 3, i16 4>
292+
; CHECK-NEXT: ret <4 x i16> [[OR]]
293293
;
294294
%t1 = trunc <4 x i32> %a to <4 x i16>
295295
%or = or <4 x i16> %t1, <i16 1, i16 2, i16 3, i16 4>
@@ -299,9 +299,9 @@ define <4 x i16> @or_trunc_v4i32_to_v4i16_constant(<4 x i32> %a) {
299299
; Test bitwise operations with zero extend and one constant
300300
define <4 x i32> @or_zext_v4i16_to_v4i32_constant(<4 x i16> %a) {
301301
; CHECK-LABEL: @or_zext_v4i16_to_v4i32_constant(
302-
; CHECK-NEXT: [[A:%.*]] = or <4 x i16> [[A1:%.*]], <i16 1, i16 2, i16 3, i16 4>
303-
; CHECK-NEXT: [[Z1:%.*]] = zext <4 x i16> [[A]] to <4 x i32>
304-
; CHECK-NEXT: ret <4 x i32> [[Z1]]
302+
; CHECK-NEXT: [[Z1:%.*]] = zext <4 x i16> [[A:%.*]] to <4 x i32>
303+
; CHECK-NEXT: [[OR:%.*]] = or <4 x i32> [[Z1]], <i32 1, i32 2, i32 3, i32 4>
304+
; CHECK-NEXT: ret <4 x i32> [[OR]]
305305
;
306306
%z1 = zext <4 x i16> %a to <4 x i32>
307307
%or = or <4 x i32> %z1, <i32 1, i32 2, i32 3, i32 4>
@@ -322,9 +322,9 @@ define <4 x i32> @or_zext_v4i8_to_v4i32_constant_with_loss(<4 x i8> %a) {
322322
; Test bitwise operations with sign extend and one constant
323323
define <4 x i32> @or_sext_v4i8_to_v4i32_positive_constant(<4 x i8> %a) {
324324
; CHECK-LABEL: @or_sext_v4i8_to_v4i32_positive_constant(
325-
; CHECK-NEXT: [[A:%.*]] = or <4 x i8> [[A1:%.*]], <i8 1, i8 2, i8 3, i8 4>
326-
; CHECK-NEXT: [[S1:%.*]] = sext <4 x i8> [[A]] to <4 x i32>
327-
; CHECK-NEXT: ret <4 x i32> [[S1]]
325+
; CHECK-NEXT: [[S1:%.*]] = sext <4 x i8> [[A:%.*]] to <4 x i32>
326+
; CHECK-NEXT: [[OR:%.*]] = or <4 x i32> [[S1]], <i32 1, i32 2, i32 3, i32 4>
327+
; CHECK-NEXT: ret <4 x i32> [[OR]]
328328
;
329329
%s1 = sext <4 x i8> %a to <4 x i32>
330330
%or = or <4 x i32> %s1, <i32 1, i32 2, i32 3, i32 4>
@@ -333,9 +333,9 @@ define <4 x i32> @or_sext_v4i8_to_v4i32_positive_constant(<4 x i8> %a) {
333333

334334
define <4 x i32> @or_sext_v4i8_to_v4i32_minus_constant(<4 x i8> %a) {
335335
; CHECK-LABEL: @or_sext_v4i8_to_v4i32_minus_constant(
336-
; CHECK-NEXT: [[A:%.*]] = or <4 x i8> [[A1:%.*]], <i8 -1, i8 -2, i8 -3, i8 -4>
337-
; CHECK-NEXT: [[S1:%.*]] = sext <4 x i8> [[A]] to <4 x i32>
338-
; CHECK-NEXT: ret <4 x i32> [[S1]]
336+
; CHECK-NEXT: [[S1:%.*]] = sext <4 x i8> [[A:%.*]] to <4 x i32>
337+
; CHECK-NEXT: [[OR:%.*]] = or <4 x i32> [[S1]], <i32 -1, i32 -2, i32 -3, i32 -4>
338+
; CHECK-NEXT: ret <4 x i32> [[OR]]
339339
;
340340
%s1 = sext <4 x i8> %a to <4 x i32>
341341
%or = or <4 x i32> %s1, <i32 -1, i32 -2, i32 -3, i32 -4>
@@ -356,9 +356,9 @@ define <4 x i32> @or_sext_v4i8_to_v4i32_constant_with_loss(<4 x i8> %a) {
356356
; Test truncate with flag preservation and one constant
357357
define <4 x i16> @and_trunc_nuw_nsw_constant(<4 x i32> %a) {
358358
; CHECK-LABEL: @and_trunc_nuw_nsw_constant(
359-
; CHECK-NEXT: [[A:%.*]] = and <4 x i32> [[A1:%.*]], <i32 1, i32 2, i32 3, i32 4>
360-
; CHECK-NEXT: [[T1:%.*]] = trunc nuw nsw <4 x i32> [[A]] to <4 x i16>
361-
; CHECK-NEXT: ret <4 x i16> [[T1]]
359+
; CHECK-NEXT: [[T1:%.*]] = trunc nuw nsw <4 x i32> [[A:%.*]] to <4 x i16>
360+
; CHECK-NEXT: [[AND:%.*]] = and <4 x i16> [[T1]], <i16 1, i16 2, i16 3, i16 4>
361+
; CHECK-NEXT: ret <4 x i16> [[AND]]
362362
;
363363
%t1 = trunc nuw nsw <4 x i32> %a to <4 x i16>
364364
%and = and <4 x i16> %t1, <i16 1, i16 2, i16 3, i16 4>
@@ -367,8 +367,8 @@ define <4 x i16> @and_trunc_nuw_nsw_constant(<4 x i32> %a) {
367367

368368
define <4 x i8> @and_trunc_nuw_nsw_minus_constant(<4 x i32> %a) {
369369
; CHECK-LABEL: @and_trunc_nuw_nsw_minus_constant(
370-
; CHECK-NEXT: [[AND_INNER:%.*]] = and <4 x i32> [[A:%.*]], <i32 240, i32 241, i32 242, i32 243>
371-
; CHECK-NEXT: [[AND:%.*]] = trunc nuw <4 x i32> [[AND_INNER]] to <4 x i8>
370+
; CHECK-NEXT: [[T1:%.*]] = trunc nuw nsw <4 x i32> [[A:%.*]] to <4 x i8>
371+
; CHECK-NEXT: [[AND:%.*]] = and <4 x i8> [[T1]], <i8 -16, i8 -15, i8 -14, i8 -13>
372372
; CHECK-NEXT: ret <4 x i8> [[AND]]
373373
;
374374
%t1 = trunc nuw nsw <4 x i32> %a to <4 x i8>
@@ -378,8 +378,8 @@ define <4 x i8> @and_trunc_nuw_nsw_minus_constant(<4 x i32> %a) {
378378

379379
define <4 x i8> @and_trunc_nuw_nsw_multiconstant(<4 x i32> %a) {
380380
; CHECK-LABEL: @and_trunc_nuw_nsw_multiconstant(
381-
; CHECK-NEXT: [[AND_INNER:%.*]] = and <4 x i32> [[A:%.*]], <i32 240, i32 1, i32 242, i32 3>
382-
; CHECK-NEXT: [[AND:%.*]] = trunc nuw <4 x i32> [[AND_INNER]] to <4 x i8>
381+
; CHECK-NEXT: [[T1:%.*]] = trunc nuw nsw <4 x i32> [[A:%.*]] to <4 x i8>
382+
; CHECK-NEXT: [[AND:%.*]] = and <4 x i8> [[T1]], <i8 -16, i8 1, i8 -14, i8 3>
383383
; CHECK-NEXT: ret <4 x i8> [[AND]]
384384
;
385385
%t1 = trunc nuw nsw <4 x i32> %a to <4 x i8>
@@ -390,9 +390,9 @@ define <4 x i8> @and_trunc_nuw_nsw_multiconstant(<4 x i32> %a) {
390390
; Test sign extend with nneg flag and one constant
391391
define <4 x i32> @or_zext_nneg_constant(<4 x i16> %a) {
392392
; CHECK-LABEL: @or_zext_nneg_constant(
393-
; CHECK-NEXT: [[A:%.*]] = or <4 x i16> [[A1:%.*]], <i16 1, i16 2, i16 3, i16 4>
394-
; CHECK-NEXT: [[Z1:%.*]] = zext nneg <4 x i16> [[A]] to <4 x i32>
395-
; CHECK-NEXT: ret <4 x i32> [[Z1]]
393+
; CHECK-NEXT: [[Z1:%.*]] = zext nneg <4 x i16> [[A:%.*]] to <4 x i32>
394+
; CHECK-NEXT: [[OR:%.*]] = or <4 x i32> [[Z1]], <i32 1, i32 2, i32 3, i32 4>
395+
; CHECK-NEXT: ret <4 x i32> [[OR]]
396396
;
397397
%z1 = zext nneg <4 x i16> %a to <4 x i32>
398398
%or = or <4 x i32> %z1, <i32 1, i32 2, i32 3, i32 4>
@@ -401,8 +401,8 @@ define <4 x i32> @or_zext_nneg_constant(<4 x i16> %a) {
401401

402402
define <4 x i32> @or_zext_nneg_minus_constant(<4 x i8> %a) {
403403
; CHECK-LABEL: @or_zext_nneg_minus_constant(
404-
; CHECK-NEXT: [[OR_INNER:%.*]] = or <4 x i8> [[A:%.*]], <i8 -16, i8 -15, i8 -14, i8 -13>
405-
; CHECK-NEXT: [[OR:%.*]] = zext <4 x i8> [[OR_INNER]] to <4 x i32>
404+
; CHECK-NEXT: [[Z1:%.*]] = zext nneg <4 x i8> [[A:%.*]] to <4 x i32>
405+
; CHECK-NEXT: [[OR:%.*]] = or <4 x i32> [[Z1]], <i32 240, i32 241, i32 242, i32 243>
406406
; CHECK-NEXT: ret <4 x i32> [[OR]]
407407
;
408408
%z1 = zext nneg <4 x i8> %a to <4 x i32>
@@ -412,8 +412,8 @@ define <4 x i32> @or_zext_nneg_minus_constant(<4 x i8> %a) {
412412

413413
define <4 x i32> @or_zext_nneg_multiconstant(<4 x i8> %a) {
414414
; CHECK-LABEL: @or_zext_nneg_multiconstant(
415-
; CHECK-NEXT: [[OR_INNER:%.*]] = or <4 x i8> [[A:%.*]], <i8 -16, i8 1, i8 -14, i8 3>
416-
; CHECK-NEXT: [[OR:%.*]] = zext <4 x i8> [[OR_INNER]] to <4 x i32>
415+
; CHECK-NEXT: [[Z1:%.*]] = zext nneg <4 x i8> [[A:%.*]] to <4 x i32>
416+
; CHECK-NEXT: [[OR:%.*]] = or <4 x i32> [[Z1]], <i32 240, i32 1, i32 242, i32 3>
417417
; CHECK-NEXT: ret <4 x i32> [[OR]]
418418
;
419419
%z1 = zext nneg <4 x i8> %a to <4 x i32>

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