Addressed the review comments3

Author: JaydeepChauhan14

llvm/lib/Target/X86/X86ISelLowering.cpp

@@ -33685,15 +33685,14 @@ void X86TargetLowering::ReplaceNodeResults(SDNode *N,
     EVT VT = N->getValueType(0);
     SDValue Op = N->getOperand(0);
     EVT OpVT = Op.getValueType();
-    SDValue V4I32;
+    SDValue Res;
 
     if (VT == MVT::v2i32 && OpVT == MVT::v2f64) {
-      SDValue V4f32 = DAG.getNode(X86ISD::VFPROUND, dl, MVT::v4f32, Op);
       if (IsSigned)
-        V4I32 = DAG.getNode(X86ISD::FP_TO_SINT_SAT, dl, MVT::v4i32, V4f32);
+        Res = DAG.getNode(X86ISD::FP_TO_SINT_SAT, dl, MVT::v4i32, Op);
       else
-        V4I32 = DAG.getNode(X86ISD::FP_TO_UINT_SAT, dl, MVT::v4i32, V4f32);
-      Results.push_back(V4I32);
+        Res = DAG.getNode(X86ISD::FP_TO_UINT_SAT, dl, MVT::v4i32, Op);
+      Results.push_back(Res);
       return;
     }
     break;
@@ -56249,15 +56248,18 @@ static SDValue combineFP_TO_xINT_SAT(SDNode *N, SelectionDAG &DAG,
   SDLoc dl(N);
 
   if (SrcVT == MVT::v2f32 && DstVT == MVT::v2i64) {
-    // Convert v2f32 to v2f64
-    SDValue V2F64 =
-        DAG.getNode(ISD::FP_EXTEND, dl, MVT::v2f64, N->getOperand(0));
+    // Create an undefined value of type v2f32
+    SDValue UndefV2F32Value = DAG.getUNDEF(MVT::v2f32);
+
+    // Concatenate the original v2f32 input and undef v2f32 to create v4f32
+    SDValue NewSrc = DAG.getNode(ISD::CONCAT_VECTORS, dl, MVT::v4f32,
+                                 N->getOperand(0), UndefV2F32Value);
 
     // Select the FP_TO_SINT_SAT/FP_TO_UINT_SAT node
     if (IsSigned)
-      return DAG.getNode(X86ISD::FP_TO_SINT_SAT, dl, MVT::v2i64, V2F64);
+      return DAG.getNode(X86ISD::FP_TO_SINT_SAT, dl, MVT::v2i64, NewSrc);
 
-    return DAG.getNode(X86ISD::FP_TO_UINT_SAT, dl, MVT::v2i64, V2F64);
+    return DAG.getNode(X86ISD::FP_TO_UINT_SAT, dl, MVT::v2i64, NewSrc);
   }
   return SDValue();
 }

llvm/lib/Target/X86/X86InstrAVX10.td

@@ -835,7 +835,7 @@ let Predicates = [HasAVX10_2] in {
 // Patterns VCVTTPD2DQSZ128
 
 // VCVTTPD2DQS
-def : Pat<(v4i32(X86fp2sisat(v4f32 VR128X:$src))),
+def : Pat<(v4i32(X86fp2sisat(v2f64 VR128X:$src))),
           (VCVTTPD2DQSZ128rr VR128X:$src)>;
 def : Pat<(v4i32(fp_to_sint_sat(v4f64 VR256X:$src), i32)),
           (VCVTTPD2DQSZ256rr VR256X:$src)>;
@@ -851,7 +851,7 @@ def : Pat<(v8i64(fp_to_sint_sat(v8f64 VR512:$src), i64)),
           (VCVTTPD2QQSZrr VR512:$src)>;
 
 // VCVTTPD2UDQS
-def : Pat<(v4i32(X86fp2uisat(v4f32 VR128X:$src))),
+def : Pat<(v4i32(X86fp2uisat(v2f64 VR128X:$src))),
           (VCVTTPD2UDQSZ128rr VR128X:$src)>;
 def : Pat<(v4i32(fp_to_uint_sat(v4f64 VR256X:$src), i32)),
           (VCVTTPD2UDQSZ256rr VR256X:$src)>;
@@ -875,7 +875,7 @@ def : Pat<(v16i32(fp_to_sint_sat(v16f32 VR512:$src), i32)),
           (VCVTTPS2DQSZrr VR512:$src)>;
 
 // VCVTTPS2QQS
-def : Pat<(v2i64(X86fp2sisat(v2f64 VR128X:$src))),
+def : Pat<(v2i64(X86fp2sisat(v4f32 VR128X:$src))),
           (VCVTTPS2QQSZ128rr VR128X:$src)>;
 def : Pat<(v4i64(fp_to_sint_sat(v4f32 VR128X:$src), i64)),
           (VCVTTPS2QQSZ256rr VR128X:$src)>;
@@ -891,7 +891,7 @@ def : Pat<(v16i32(fp_to_uint_sat(v16f32 VR512:$src), i32)),
           (VCVTTPS2UDQSZrr VR512:$src)>;
 
 // VCVTTPS2UQQS
-def : Pat<(v2i64(X86fp2uisat(v2f64 VR128X:$src))),
+def : Pat<(v2i64(X86fp2uisat(v4f32 VR128X:$src))),
           (VCVTTPS2UQQSZ128rr VR128X:$src)>;
 def : Pat<(v4i64(fp_to_uint_sat(v4f32 VR128X:$src), i64)),
           (VCVTTPS2UQQSZ256rr VR128X:$src)>;

llvm/test/CodeGen/X86/avx10_2fptosi_satcvtds.ll

@@ -117,7 +117,6 @@ define i64 @test_signed_i64_f64(double %f) nounwind {
 define <2 x i32> @test_signed_v2i32_v2f64(<2 x double> %d) nounwind {
 ; CHECK-LABEL: test_signed_v2i32_v2f64:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vcvtpd2ps %xmm0, %xmm0
 ; CHECK-NEXT:    vcvttpd2dqs %xmm0, %xmm0
 ; CHECK-NEXT:    ret{{[l|q]}}
   %x = call  <2 x i32> @llvm.fptosi.sat.v2i32.v2f64(<2 x double> %d)
@@ -157,7 +156,6 @@ define <4 x i64> @test_signed_v4i64_v4f64(<4 x double> %f) nounwind {
 define <2 x i32> @test_unsigned_v2i32_v2f64(<2 x double> %d) nounwind {
 ; CHECK-LABEL: test_unsigned_v2i32_v2f64:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vcvtpd2ps %xmm0, %xmm0
 ; CHECK-NEXT:    vcvttpd2udqs %xmm0, %xmm0
 ; CHECK-NEXT:    ret{{[l|q]}}
   %x = call  <2 x i32> @llvm.fptoui.sat.v2i32.v2f64(<2 x double> %d)
@@ -235,7 +233,6 @@ define <8 x i32> @test_unsigned_v8i32_v8f32(<8 x float> %f) nounwind {
 define <2 x i64> @test_signed_v2i64_v2f32(<2 x float> %f) nounwind {
 ; CHECK-LABEL: test_signed_v2i64_v2f32:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vcvtps2pd %xmm0, %xmm0
 ; CHECK-NEXT:    vcvttps2qqs %xmm0, %xmm0
 ; CHECK-NEXT:    ret{{[l|q]}}
   %x = call  <2 x i64> @llvm.fptosi.sat.v2i64.v2f32(<2 x float> %f)
@@ -255,7 +252,6 @@ define <4 x i64> @test_signed_v4i64_v4f32(<4 x float> %f) nounwind {
 define <2 x i64> @test_unsigned_v2i64_v2f32(<2 x float> %f) nounwind {
 ; CHECK-LABEL: test_unsigned_v2i64_v2f32:
 ; CHECK:       # %bb.0:
-; CHECK-NEXT:    vcvtps2pd %xmm0, %xmm0
 ; CHECK-NEXT:    vcvttps2uqqs %xmm0, %xmm0
 ; CHECK-NEXT:    ret{{[l|q]}}
   %x = call  <2 x i64> @llvm.fptoui.sat.v2i64.v2f32(<2 x float> %f)