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Merging r359834:
------------------------------------------------------------------------ r359834 | evandro | 2019-05-02 15:01:39 -0700 (Thu, 02 May 2019) | 3 lines [AArch64] Update for Exynos Fix the forwarding of multiplication results for Exynos M4. ------------------------------------------------------------------------ llvm-svn: 359946
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‎llvm/lib/Target/AArch64/AArch64SchedExynosM4.td

Lines changed: 18 additions & 18 deletions
Original file line numberDiff line numberDiff line change
@@ -239,7 +239,6 @@ def M4WriteNEONK : SchedWriteRes<[M4UnitNSHF,
239239
M4UnitS0]> { let Latency = 5;
240240
let NumMicroOps = 2; }
241241
def M4WriteNEONL : SchedWriteRes<[M4UnitNMUL]> { let Latency = 3; }
242-
def M4WriteNEONM : SchedWriteRes<[M4UnitNMUL]> { let Latency = 3; }
243242
def M4WriteNEONN : SchedWriteRes<[M4UnitNMSC,
244243
M4UnitNMSC]> { let Latency = 5;
245244
let NumMicroOps = 2; }
@@ -480,16 +479,15 @@ def M4WriteCOPY : SchedWriteVariant<[SchedVar<ExynosFPPred, [M4WriteNALU1]>,
480479
SchedVar<NoSchedPred, [M4WriteZ0]>]>;
481480
def M4WriteMOVI : SchedWriteVariant<[SchedVar<IsZeroFPIdiomPred, [M4WriteZ0]>,
482481
SchedVar<NoSchedPred, [M4WriteNALU1]>]>;
483-
def M4WriteMULL : SchedWriteVariant<[SchedVar<ExynosLongVectorUpperPred, [M4WriteNEONM]>,
484-
SchedVar<NoSchedPred, [M4WriteNMUL3]>]>;
485482

486483
// Fast forwarding.
487484
def M4ReadAESM1 : SchedReadAdvance<+1, [M4WriteNCRY1]>;
488485
def M4ReadFMACM1 : SchedReadAdvance<+1, [M4WriteFMAC4,
489486
M4WriteFMAC4H,
490487
M4WriteFMAC5]>;
491488
def M4ReadNMULM1 : SchedReadAdvance<+1, [M4WriteNMUL3]>;
492-
def M4ReadMULLP2 : SchedReadAdvance<-2, [M4WriteNEONM]>;
489+
def M4ReadNMULP2 : SchedReadAdvance<-2, [M4WriteNMUL3]>;
490+
493491

494492
//===----------------------------------------------------------------------===//
495493
// Coarse scheduling model.
@@ -662,10 +660,8 @@ def : InstRW<[M4WriteNEONK], (instregex "^FMOVDXHighr")>;
662660
def : InstRW<[M4WriteFCVT3H], (instregex "^F(RECP|RSQRT)Ev1f16")>;
663661
def : InstRW<[M4WriteFCVT3], (instregex "^F(RECP|RSQRT)Ev1i(32|64)")>;
664662
def : InstRW<[M4WriteNMSC1], (instregex "^FRECPXv1")>;
665-
def : InstRW<[M4WriteFMAC4H,
666-
M4ReadFMACM1], (instregex "^F(RECP|RSQRT)S16")>;
667-
def : InstRW<[M4WriteFMAC4,
668-
M4ReadFMACM1], (instregex "^F(RECP|RSQRT)S(32|64)")>;
663+
def : InstRW<[M4WriteFMAC4H], (instregex "^F(RECP|RSQRT)S16")>;
664+
def : InstRW<[M4WriteFMAC4], (instregex "^F(RECP|RSQRT)S(32|64)")>;
669665

670666
// FP load instructions.
671667
def : InstRW<[WriteVLD], (instregex "^LDR[SDQ]l")>;
@@ -736,14 +732,20 @@ def : InstRW<[M4WriteNALU1], (instregex "^(AND|BIC|EOR|NOT|ORN|ORR)v")>;
736732
def : InstRW<[M4WriteNMSC1], (instregex "^[SU](MIN|MAX)v")>;
737733
def : InstRW<[M4WriteNMSC2], (instregex "^[SU](MIN|MAX)Pv")>;
738734
def : InstRW<[M4WriteNHAD3], (instregex "^[SU](MIN|MAX)Vv")>;
739-
def : InstRW<[M4WriteNMUL3], (instregex "^(SQR?D)?MULH?v")>;
740735
def : InstRW<[M4WriteNMUL3,
741736
M4ReadNMULM1], (instregex "^ML[AS]v")>;
742-
def : InstRW<[M4WriteNMUL3], (instregex "^SQRDML[AS]H")>;
743-
def : InstRW<[M4WriteMULL,
744-
M4ReadMULLP2], (instregex "^(S|U|SQD)ML[AS]Lv")>;
745-
def : InstRW<[M4WriteMULL,
746-
M4ReadMULLP2], (instregex "^(S|U|SQD)MULLv")>;
737+
def : InstRW<[M4WriteNMUL3,
738+
M4ReadNMULM1], (instregex "^(SQR?D)?MULH?v")>;
739+
def : InstRW<[M4WriteNMUL3,
740+
M4ReadNMULM1], (instregex "^SQRDML[AS]H")>;
741+
def : InstRW<[M4WriteNMUL3,
742+
M4ReadNMULM1], (instregex "^(S|U|SQD)ML[AS]L(v1(i32|i64)|v2i32|v4i16|v8i8)")>;
743+
def : InstRW<[M4WriteNMUL3,
744+
M4ReadNMULP2], (instregex "^(S|U|SQD)ML[AS]L(v4i32|v8i16|v16i8)")>;
745+
def : InstRW<[M4WriteNMUL3,
746+
M4ReadNMULM1], (instregex "^(S|U|SQD)MULL(v1(i32|i64)|v2i32|v4i16|v8i8)")>;
747+
def : InstRW<[M4WriteNMUL3,
748+
M4ReadNMULP2], (instregex "^(S|U|SQD)MULL(v4i32|v8i16|v16i8)")>;
747749
def : InstRW<[M4WriteNMUL3], (instregex "^[SU]DOT(lane)?v")>;
748750
def : InstRW<[M4WriteNHAD3], (instregex "^[SU]ADALPv")>;
749751
def : InstRW<[M4WriteNSHT4A], (instregex "^[SU]R?SRA[dv]")>;
@@ -808,10 +810,8 @@ def : InstRW<[M4WriteNALU1], (instregex "^FMOVv.f(32|64)")>;
808810
def : InstRW<[M4WriteFCVT3H], (instregex "^F(RECP|RSQRT)Ev[248]f16")>;
809811
def : InstRW<[M4WriteFCVT3], (instregex "^F(RECP|RSQRT)Ev[248]f(32|64)")>;
810812
def : InstRW<[M4WriteFCVT3], (instregex "^U(RECP|RSQRT)Ev[24]i32")>;
811-
def : InstRW<[M4WriteFMAC4H,
812-
M4ReadFMACM1], (instregex "^F(RECP|RSQRT)Sv.f16")>;
813-
def : InstRW<[M4WriteFMAC4,
814-
M4ReadFMACM1], (instregex "^F(RECP|RSQRT)Sv.f(32|64)")>;
813+
def : InstRW<[M4WriteFMAC4H], (instregex "^F(RECP|RSQRT)Sv.f16")>;
814+
def : InstRW<[M4WriteFMAC4], (instregex "^F(RECP|RSQRT)Sv.f(32|64)")>;
815815
def : InstRW<[M4WriteNSHF1], (instregex "^REV(16|32|64)v")>;
816816
def : InstRW<[M4WriteNSHFA], (instregex "^TB[LX]v(8|16)i8One")>;
817817
def : InstRW<[M4WriteNSHFB], (instregex "^TB[LX]v(8|16)i8Two")>;

‎llvm/lib/Target/AArch64/AArch64SchedPredExynos.td

Lines changed: 0 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -103,17 +103,6 @@ def ExynosScaledIdxPred : MCSchedPredicate<ExynosScaledIdxFn>;
103103
// Identify FP instructions.
104104
def ExynosFPPred : MCSchedPredicate<CheckAny<[CheckDForm, CheckQForm]>>;
105105

106-
// Identify whether an instruction whose result is a long vector
107-
// operates on the upper half of the input registers.
108-
def ExynosLongVectorUpperFn : TIIPredicate<
109-
"isExynosLongVectorUpper",
110-
MCOpcodeSwitchStatement<
111-
[MCOpcodeSwitchCase<
112-
IsLongVectorUpperOp.ValidOpcodes,
113-
MCReturnStatement<TruePred>>],
114-
MCReturnStatement<FalsePred>>>;
115-
def ExynosLongVectorUpperPred : MCSchedPredicate<ExynosLongVectorUpperFn>;
116-
117106
// Identify 128-bit NEON instructions.
118107
def ExynosQFormPred : MCSchedPredicate<CheckQForm>;
119108

‎llvm/lib/Target/AArch64/AArch64SchedPredicates.td

Lines changed: 0 additions & 53 deletions
Original file line numberDiff line numberDiff line change
@@ -268,59 +268,6 @@ def IsStoreRegOffsetOp : CheckOpcode<[STRBBroW, STRBBroX,
268268
def IsLoadStoreRegOffsetOp : CheckOpcode<!listconcat(IsLoadRegOffsetOp.ValidOpcodes,
269269
IsStoreRegOffsetOp.ValidOpcodes)>;
270270

271-
// Identify whether an instruction whose result is a long vector
272-
// operates on the upper half of the input registers.
273-
def IsLongVectorUpperOp : CheckOpcode<[FCVTLv8i16, FCVTLv4i32,
274-
FCVTNv8i16, FCVTNv4i32,
275-
FCVTXNv4f32,
276-
PMULLv16i8, PMULLv2i64,
277-
RADDHNv8i16_v16i8, RADDHNv4i32_v8i16, RADDHNv2i64_v4i32,
278-
RSHRNv16i8_shift, RSHRNv8i16_shift, RSHRNv4i32_shift,
279-
RSUBHNv8i16_v16i8, RSUBHNv4i32_v8i16, RSUBHNv2i64_v4i32,
280-
SABALv16i8_v8i16, SABALv8i16_v4i32, SABALv4i32_v2i64,
281-
SABDLv16i8_v8i16, SABDLv8i16_v4i32, SABDLv4i32_v2i64,
282-
SADDLv16i8_v8i16, SADDLv8i16_v4i32, SADDLv4i32_v2i64,
283-
SADDWv16i8_v8i16, SADDWv8i16_v4i32, SADDWv4i32_v2i64,
284-
SHLLv16i8, SHLLv8i16, SHLLv4i32,
285-
SHRNv16i8_shift, SHRNv8i16_shift, SHRNv4i32_shift,
286-
SMLALv16i8_v8i16, SMLALv8i16_v4i32, SMLALv4i32_v2i64,
287-
SMLALv8i16_indexed, SMLALv4i32_indexed,
288-
SMLSLv16i8_v8i16, SMLSLv8i16_v4i32, SMLSLv4i32_v2i64,
289-
SMLSLv8i16_indexed, SMLSLv4i32_indexed,
290-
SMULLv16i8_v8i16, SMULLv8i16_v4i32, SMULLv4i32_v2i64,
291-
SMULLv8i16_indexed, SMULLv4i32_indexed,
292-
SQDMLALv8i16_v4i32, SQDMLALv4i32_v2i64,
293-
SQDMLALv8i16_indexed, SQDMLALv4i32_indexed,
294-
SQDMLSLv8i16_v4i32, SQDMLSLv4i32_v2i64,
295-
SQDMLSLv8i16_indexed, SQDMLSLv4i32_indexed,
296-
SQDMULLv8i16_v4i32, SQDMULLv4i32_v2i64,
297-
SQDMULLv8i16_indexed, SQDMULLv4i32_indexed,
298-
SQRSHRNv16i8_shift, SQRSHRNv8i16_shift, SQRSHRNv4i32_shift,
299-
SQRSHRUNv16i8_shift, SQRSHRUNv8i16_shift, SQRSHRUNv4i32_shift,
300-
SQSHRNv16i8_shift, SQSHRNv8i16_shift, SQSHRNv4i32_shift,
301-
SQSHRUNv16i8_shift, SQSHRUNv8i16_shift, SQSHRUNv4i32_shift,
302-
SQXTNv16i8, SQXTNv8i16, SQXTNv4i32,
303-
SQXTUNv16i8, SQXTUNv8i16, SQXTUNv4i32,
304-
SSHLLv16i8_shift, SSHLLv8i16_shift, SSHLLv4i32_shift,
305-
SSUBLv16i8_v8i16, SSUBLv8i16_v4i32, SSUBLv4i32_v2i64,
306-
SSUBWv16i8_v8i16, SSUBWv8i16_v4i32, SSUBWv4i32_v2i64,
307-
UABALv16i8_v8i16, UABALv8i16_v4i32, UABALv4i32_v2i64,
308-
UABDLv16i8_v8i16, UABDLv8i16_v4i32, UABDLv4i32_v2i64,
309-
UADDLv16i8_v8i16, UADDLv8i16_v4i32, UADDLv4i32_v2i64,
310-
UADDWv16i8_v8i16, UADDWv8i16_v4i32, UADDWv4i32_v2i64,
311-
UMLALv16i8_v8i16, UMLALv8i16_v4i32, UMLALv4i32_v2i64,
312-
UMLALv8i16_indexed, UMLALv4i32_indexed,
313-
UMLSLv16i8_v8i16, UMLSLv8i16_v4i32, UMLSLv4i32_v2i64,
314-
UMLSLv8i16_indexed, UMLSLv4i32_indexed,
315-
UMULLv16i8_v8i16, UMULLv8i16_v4i32, UMULLv4i32_v2i64,
316-
UMULLv8i16_indexed, UMULLv4i32_indexed,
317-
UQSHRNv16i8_shift, UQSHRNv8i16_shift, UQSHRNv4i32_shift,
318-
UQXTNv16i8, UQXTNv8i16, UQXTNv4i32,
319-
USHLLv16i8_shift, USHLLv8i16_shift, USHLLv4i32_shift,
320-
USUBLv16i8_v8i16, USUBLv8i16_v4i32, USUBLv4i32_v2i64,
321-
USUBWv16i8_v8i16, USUBWv8i16_v4i32, USUBWv4i32_v2i64,
322-
XTNv16i8, XTNv8i16, XTNv4i32]>;
323-
324271
// Target predicates.
325272

326273
// Identify an instruction that effectively transfers a register to another.

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