[RISCV] Add support for -mtune=andes-45-series (#142900)

Enables the use of `-mtune=andes-45-series` to generate code optimized
with the Andes 45 series scheduling model and tuning features.

Author: tclin914

clang/test/Misc/target-invalid-cpu-note/riscv.c

@@ -77,6 +77,7 @@
 // TUNE-RISCV32-SAME: {{^}}, syntacore-scr3-rv32
 // TUNE-RISCV32-SAME: {{^}}, syntacore-scr4-rv32
 // TUNE-RISCV32-SAME: {{^}}, syntacore-scr5-rv32
+// TUNE-RISCV32-SAME: {{^}}, andes-45-series
 // TUNE-RISCV32-SAME: {{^}}, generic
 // TUNE-RISCV32-SAME: {{^}}, generic-ooo
 // TUNE-RISCV32-SAME: {{^}}, rocket
@@ -114,6 +115,7 @@
 // TUNE-RISCV64-SAME: {{^}}, veyron-v1
 // TUNE-RISCV64-SAME: {{^}}, xiangshan-kunminghu
 // TUNE-RISCV64-SAME: {{^}}, xiangshan-nanhu
+// TUNE-RISCV64-SAME: {{^}}, andes-45-series
 // TUNE-RISCV64-SAME: {{^}}, generic
 // TUNE-RISCV64-SAME: {{^}}, generic-ooo
 // TUNE-RISCV64-SAME: {{^}}, rocket

llvm/docs/ReleaseNotes.md

@@ -209,6 +209,7 @@ Changes to the RISC-V Backend
 * `-mcpu=andes-a25` and `-mcpu=andes-ax25` were added.
 * The `Shlcofideleg` extension was added.
 * `-mcpu=sifive-x390` was added.
+* `-mtune=andes-45-series` was added.
 
 Changes to the WebAssembly Backend
 ----------------------------------

llvm/lib/Target/RISCV/RISCVProcessors.td

@@ -722,6 +722,9 @@ def ANDES_AX25 : RISCVProcessorModel<"andes-ax25",
                                       FeatureStdExtZbc,
                                       FeatureVendorXAndesPerf]>;
 
+def ANDES_45 : RISCVTuneProcessorModel<"andes-45-series",
+                                       Andes45Model>;
+
 def ANDES_N45 : RISCVProcessorModel<"andes-n45",
                                     Andes45Model,
                                     [Feature32Bit,