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RKSimonRKSimon
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[X86] vector-shift tests - regenerate VPTERNLOG comments
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6 files changed

+30
-30
lines changed

6 files changed

+30
-30
lines changed

‎llvm/test/CodeGen/X86/vector-shift-ashr-128.ll‎

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -1553,7 +1553,7 @@ define <8 x i16> @constant_shift_v8i16_pairs(<8 x i16> %a) nounwind {
15531553
; AVX512DQVL: # %bb.0:
15541554
; AVX512DQVL-NEXT: vpsrlvd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
15551555
; AVX512DQVL-NEXT: vmovdqa {{.*#+}} xmm1 = [256,256,16384,16384,4096,4096,512,512]
1556-
; AVX512DQVL-NEXT: vpternlogq $108, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm0
1556+
; AVX512DQVL-NEXT: vpternlogq {{.*#+}} xmm0 = xmm1 ^ (xmm0 & mem)
15571557
; AVX512DQVL-NEXT: vpsubw %xmm1, %xmm0, %xmm0
15581558
; AVX512DQVL-NEXT: retq
15591559
;
@@ -1734,15 +1734,15 @@ define <16 x i8> @constant_shift_v16i8_pairs(<16 x i8> %a) nounwind {
17341734
; AVX512DQVL-NEXT: vpmulhuw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1 # [32768,4096,512,8192,16384,u,2048,1024]
17351735
; AVX512DQVL-NEXT: vpblendw {{.*#+}} xmm0 = xmm1[0,1,2,3,4],xmm0[5],xmm1[6,7]
17361736
; AVX512DQVL-NEXT: vmovdqa {{.*#+}} xmm1 = [64,64,8,8,1,1,16,16,32,32,128,128,4,4,2,2]
1737-
; AVX512DQVL-NEXT: vpternlogq $108, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm0
1737+
; AVX512DQVL-NEXT: vpternlogq {{.*#+}} xmm0 = xmm1 ^ (xmm0 & mem)
17381738
; AVX512DQVL-NEXT: vpsubb %xmm1, %xmm0, %xmm0
17391739
; AVX512DQVL-NEXT: retq
17401740
;
17411741
; AVX512BWVL-LABEL: constant_shift_v16i8_pairs:
17421742
; AVX512BWVL: # %bb.0:
17431743
; AVX512BWVL-NEXT: vpsrlvw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
17441744
; AVX512BWVL-NEXT: vmovdqa {{.*#+}} xmm1 = [64,64,8,8,1,1,16,16,32,32,128,128,4,4,2,2]
1745-
; AVX512BWVL-NEXT: vpternlogq $108, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm0
1745+
; AVX512BWVL-NEXT: vpternlogq {{.*#+}} xmm0 = xmm1 ^ (xmm0 & mem)
17461746
; AVX512BWVL-NEXT: vpsubb %xmm1, %xmm0, %xmm0
17471747
; AVX512BWVL-NEXT: retq
17481748
;
@@ -1822,7 +1822,7 @@ define <16 x i8> @constant_shift_v16i8_quads(<16 x i8> %a) nounwind {
18221822
; AVX512VL: # %bb.0:
18231823
; AVX512VL-NEXT: vpsrlvd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
18241824
; AVX512VL-NEXT: vmovdqa {{.*#+}} xmm1 = [128,128,128,128,64,64,64,64,16,16,16,16,32,32,32,32]
1825-
; AVX512VL-NEXT: vpternlogq $108, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm0
1825+
; AVX512VL-NEXT: vpternlogq {{.*#+}} xmm0 = xmm1 ^ (xmm0 & mem)
18261826
; AVX512VL-NEXT: vpsubb %xmm1, %xmm0, %xmm0
18271827
; AVX512VL-NEXT: retq
18281828
;
@@ -2021,15 +2021,15 @@ define <16 x i8> @splatconstant_shift_v16i8(<16 x i8> %a) nounwind {
20212021
; AVX512DQVL: # %bb.0:
20222022
; AVX512DQVL-NEXT: vpsrlw $3, %xmm0, %xmm0
20232023
; AVX512DQVL-NEXT: vpbroadcastd {{.*#+}} xmm1 = [16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16]
2024-
; AVX512DQVL-NEXT: vpternlogd $108, {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm1, %xmm0
2024+
; AVX512DQVL-NEXT: vpternlogd {{.*#+}} xmm0 = xmm1 ^ (xmm0 & mem)
20252025
; AVX512DQVL-NEXT: vpsubb %xmm1, %xmm0, %xmm0
20262026
; AVX512DQVL-NEXT: retq
20272027
;
20282028
; AVX512BWVL-LABEL: splatconstant_shift_v16i8:
20292029
; AVX512BWVL: # %bb.0:
20302030
; AVX512BWVL-NEXT: vpsrlw $3, %xmm0, %xmm0
20312031
; AVX512BWVL-NEXT: vpbroadcastb {{.*#+}} xmm1 = [16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16]
2032-
; AVX512BWVL-NEXT: vpternlogd $108, {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm1, %xmm0
2032+
; AVX512BWVL-NEXT: vpternlogd {{.*#+}} xmm0 = xmm1 ^ (xmm0 & mem)
20332033
; AVX512BWVL-NEXT: vpsubb %xmm1, %xmm0, %xmm0
20342034
; AVX512BWVL-NEXT: retq
20352035
;

‎llvm/test/CodeGen/X86/vector-shift-ashr-256.ll‎

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -952,7 +952,7 @@ define <32 x i8> @splatvar_shift_v32i8(<32 x i8> %a, <32 x i8> %b) nounwind {
952952
; AVX512DQVL-NEXT: vpsrlw %xmm1, %xmm3, %xmm1
953953
; AVX512DQVL-NEXT: vpsrlw $8, %xmm1, %xmm1
954954
; AVX512DQVL-NEXT: vpbroadcastb %xmm1, %ymm1
955-
; AVX512DQVL-NEXT: vpternlogq $108, %ymm0, %ymm2, %ymm1
955+
; AVX512DQVL-NEXT: vpternlogq {{.*#+}} ymm1 = ymm2 ^ (ymm1 & ymm0)
956956
; AVX512DQVL-NEXT: vpsubb %ymm2, %ymm1, %ymm0
957957
; AVX512DQVL-NEXT: retq
958958
;
@@ -1321,7 +1321,7 @@ define <32 x i8> @splatvar_modulo_shift_v32i8(<32 x i8> %a, <32 x i8> %b) nounwi
13211321
; AVX512DQVL-NEXT: vpsrlw %xmm1, %xmm3, %xmm1
13221322
; AVX512DQVL-NEXT: vpsrlw $8, %xmm1, %xmm1
13231323
; AVX512DQVL-NEXT: vpbroadcastb %xmm1, %ymm1
1324-
; AVX512DQVL-NEXT: vpternlogq $108, %ymm0, %ymm2, %ymm1
1324+
; AVX512DQVL-NEXT: vpternlogq {{.*#+}} ymm1 = ymm2 ^ (ymm1 & ymm0)
13251325
; AVX512DQVL-NEXT: vpsubb %ymm2, %ymm1, %ymm0
13261326
; AVX512DQVL-NEXT: retq
13271327
;
@@ -1681,7 +1681,7 @@ define <16 x i16> @constant_shift_v16i16_pairs(<16 x i16> %a) nounwind {
16811681
; AVX512DQVL: # %bb.0:
16821682
; AVX512DQVL-NEXT: vpsrlvd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
16831683
; AVX512DQVL-NEXT: vmovdqa {{.*#+}} ymm1 = [32768,32768,16384,16384,4096,4096,8192,8192,512,512,256,256,1024,1024,2048,2048]
1684-
; AVX512DQVL-NEXT: vpternlogq $108, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm0
1684+
; AVX512DQVL-NEXT: vpternlogq {{.*#+}} ymm0 = ymm1 ^ (ymm0 & mem)
16851685
; AVX512DQVL-NEXT: vpsubw %ymm1, %ymm0, %ymm0
16861686
; AVX512DQVL-NEXT: retq
16871687
;
@@ -1926,15 +1926,15 @@ define <32 x i8> @constant_shift_v32i8_pairs(<32 x i8> %a) nounwind {
19261926
; AVX512DQVL-NEXT: vpblendw {{.*#+}} xmm0 = xmm1[0,1,2,3,4,5,6],xmm0[7]
19271927
; AVX512DQVL-NEXT: vpblendd {{.*#+}} ymm0 = ymm0[0,1,2,3],ymm1[4,5,6,7]
19281928
; AVX512DQVL-NEXT: vmovdqa {{.*#+}} ymm1 = [4,4,2,2,4,4,8,8,32,32,2,2,32,32,128,128,1,1,32,32,8,8,2,2,16,16,4,4,8,8,64,64]
1929-
; AVX512DQVL-NEXT: vpternlogq $108, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm0
1929+
; AVX512DQVL-NEXT: vpternlogq {{.*#+}} ymm0 = ymm1 ^ (ymm0 & mem)
19301930
; AVX512DQVL-NEXT: vpsubb %ymm1, %ymm0, %ymm0
19311931
; AVX512DQVL-NEXT: retq
19321932
;
19331933
; AVX512BWVL-LABEL: constant_shift_v32i8_pairs:
19341934
; AVX512BWVL: # %bb.0:
19351935
; AVX512BWVL-NEXT: vpsrlvw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
19361936
; AVX512BWVL-NEXT: vmovdqa {{.*#+}} ymm1 = [4,4,2,2,4,4,8,8,32,32,2,2,32,32,128,128,1,1,32,32,8,8,2,2,16,16,4,4,8,8,64,64]
1937-
; AVX512BWVL-NEXT: vpternlogq $108, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm0
1937+
; AVX512BWVL-NEXT: vpternlogq {{.*#+}} ymm0 = ymm1 ^ (ymm0 & mem)
19381938
; AVX512BWVL-NEXT: vpsubb %ymm1, %ymm0, %ymm0
19391939
; AVX512BWVL-NEXT: retq
19401940
;
@@ -2025,7 +2025,7 @@ define <32 x i8> @constant_shift_v32i8_quads(<32 x i8> %a) nounwind {
20252025
; AVX512VL: # %bb.0:
20262026
; AVX512VL-NEXT: vpsrlvd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
20272027
; AVX512VL-NEXT: vmovdqa {{.*#+}} ymm1 = [128,128,128,128,64,64,64,64,16,16,16,16,32,32,32,32,2,2,2,2,1,1,1,1,4,4,4,4,8,8,8,8]
2028-
; AVX512VL-NEXT: vpternlogq $108, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm0
2028+
; AVX512VL-NEXT: vpternlogq {{.*#+}} ymm0 = ymm1 ^ (ymm0 & mem)
20292029
; AVX512VL-NEXT: vpsubb %ymm1, %ymm0, %ymm0
20302030
; AVX512VL-NEXT: retq
20312031
;
@@ -2295,15 +2295,15 @@ define <32 x i8> @splatconstant_shift_v32i8(<32 x i8> %a) nounwind {
22952295
; AVX512DQVL: # %bb.0:
22962296
; AVX512DQVL-NEXT: vpsrlw $3, %ymm0, %ymm0
22972297
; AVX512DQVL-NEXT: vpbroadcastd {{.*#+}} ymm1 = [16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16]
2298-
; AVX512DQVL-NEXT: vpternlogd $108, {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %ymm1, %ymm0
2298+
; AVX512DQVL-NEXT: vpternlogd {{.*#+}} ymm0 = ymm1 ^ (ymm0 & mem)
22992299
; AVX512DQVL-NEXT: vpsubb %ymm1, %ymm0, %ymm0
23002300
; AVX512DQVL-NEXT: retq
23012301
;
23022302
; AVX512BWVL-LABEL: splatconstant_shift_v32i8:
23032303
; AVX512BWVL: # %bb.0:
23042304
; AVX512BWVL-NEXT: vpsrlw $3, %ymm0, %ymm0
23052305
; AVX512BWVL-NEXT: vpbroadcastb {{.*#+}} ymm1 = [16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16]
2306-
; AVX512BWVL-NEXT: vpternlogd $108, {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %ymm1, %ymm0
2306+
; AVX512BWVL-NEXT: vpternlogd {{.*#+}} ymm0 = ymm1 ^ (ymm0 & mem)
23072307
; AVX512BWVL-NEXT: vpsubb %ymm1, %ymm0, %ymm0
23082308
; AVX512BWVL-NEXT: retq
23092309
;

‎llvm/test/CodeGen/X86/vector-shift-ashr-512.ll‎

Lines changed: 7 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -218,7 +218,7 @@ define <64 x i8> @splatvar_shift_v64i8(<64 x i8> %a, <64 x i8> %b) nounwind {
218218
; AVX512BW-NEXT: vpsrlw %xmm1, %xmm3, %xmm1
219219
; AVX512BW-NEXT: vpsrlw $8, %xmm1, %xmm1
220220
; AVX512BW-NEXT: vpbroadcastb %xmm1, %zmm1
221-
; AVX512BW-NEXT: vpternlogq $108, %zmm0, %zmm2, %zmm1
221+
; AVX512BW-NEXT: vpternlogq {{.*#+}} zmm1 = zmm2 ^ (zmm1 & zmm0)
222222
; AVX512BW-NEXT: vpsubb %zmm2, %zmm1, %zmm0
223223
; AVX512BW-NEXT: retq
224224
%splat = shufflevector <64 x i8> %b, <64 x i8> poison, <64 x i32> zeroinitializer
@@ -307,7 +307,7 @@ define <64 x i8> @splatvar_modulo_shift_v64i8(<64 x i8> %a, <64 x i8> %b) nounwi
307307
; AVX512BW-NEXT: vpsrlw %xmm1, %xmm3, %xmm1
308308
; AVX512BW-NEXT: vpsrlw $8, %xmm1, %xmm1
309309
; AVX512BW-NEXT: vpbroadcastb %xmm1, %zmm1
310-
; AVX512BW-NEXT: vpternlogq $108, %zmm0, %zmm2, %zmm1
310+
; AVX512BW-NEXT: vpternlogq {{.*#+}} zmm1 = zmm2 ^ (zmm1 & zmm0)
311311
; AVX512BW-NEXT: vpsubb %zmm2, %zmm1, %zmm0
312312
; AVX512BW-NEXT: retq
313313
%mod = and <64 x i8> %b, <i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7>
@@ -365,7 +365,7 @@ define <32 x i16> @constant_shift_v32i16_pairs(<32 x i16> %a) nounwind {
365365
; AVX512DQ: # %bb.0:
366366
; AVX512DQ-NEXT: vpsrlvd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm0
367367
; AVX512DQ-NEXT: vmovdqa64 {{.*#+}} zmm1 = [128,128,128,128,64,64,64,64,32,32,32,32,16,16,16,16,8,8,8,8,4,4,4,4,2,2,2,2,1,1,1,1]
368-
; AVX512DQ-NEXT: vpternlogq $108, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm1, %zmm0
368+
; AVX512DQ-NEXT: vpternlogq {{.*#+}} zmm0 = zmm1 ^ (zmm0 & mem)
369369
; AVX512DQ-NEXT: vpsubw %ymm1, %ymm0, %ymm1
370370
; AVX512DQ-NEXT: vextracti64x4 $1, %zmm0, %ymm0
371371
; AVX512DQ-NEXT: vpsubw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
@@ -450,7 +450,7 @@ define <64 x i8> @constant_shift_v64i8_pairs(<64 x i8> %a) nounwind {
450450
; AVX512BW: # %bb.0:
451451
; AVX512BW-NEXT: vpsrlvw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm0
452452
; AVX512BW-NEXT: vmovdqa64 {{.*#+}} zmm1 = [2,2,2,2,32,32,32,32,2,2,8,8,8,8,4,4,2,2,64,64,16,16,32,32,8,8,1,1,4,4,128,128,1,1,64,64,128,128,1,1,8,8,128,128,64,64,16,16,64,64,8,8,8,8,16,16,2,2,2,2,4,4,2,2]
453-
; AVX512BW-NEXT: vpternlogq $108, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm1, %zmm0
453+
; AVX512BW-NEXT: vpternlogq {{.*#+}} zmm0 = zmm1 ^ (zmm0 & mem)
454454
; AVX512BW-NEXT: vpsubb %zmm1, %zmm0, %zmm0
455455
; AVX512BW-NEXT: retq
456456
%shift = ashr <64 x i8> %a, <i8 6, i8 6, i8 6, i8 6, i8 2, i8 2, i8 2, i8 2, i8 6, i8 6, i8 4, i8 4, i8 4, i8 4, i8 5, i8 5, i8 6, i8 6, i8 1, i8 1, i8 3, i8 3, i8 2, i8 2, i8 4, i8 4, i8 7, i8 7, i8 5, i8 5, i8 0, i8 0, i8 7, i8 7, i8 1, i8 1, i8 0, i8 0, i8 7, i8 7, i8 4, i8 4, i8 0, i8 0, i8 1, i8 1, i8 3, i8 3, i8 1, i8 1, i8 4, i8 4, i8 4, i8 4, i8 3, i8 3, i8 6, i8 6, i8 6, i8 6, i8 5, i8 5, i8 6, i8 6>
@@ -462,7 +462,7 @@ define <64 x i8> @constant_shift_v64i8_quads(<64 x i8> %a) nounwind {
462462
; AVX512DQ: # %bb.0:
463463
; AVX512DQ-NEXT: vpsrlvd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm0
464464
; AVX512DQ-NEXT: vmovdqa64 {{.*#+}} zmm1 = [16,16,16,16,4,4,4,4,32,32,32,32,1,1,1,1,1,1,1,1,4,4,4,4,1,1,1,1,4,4,4,4,8,8,8,8,16,16,16,16,16,16,16,16,2,2,2,2,64,64,64,64,4,4,4,4,32,32,32,32,128,128,128,128]
465-
; AVX512DQ-NEXT: vpternlogq $108, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm1, %zmm0
465+
; AVX512DQ-NEXT: vpternlogq {{.*#+}} zmm0 = zmm1 ^ (zmm0 & mem)
466466
; AVX512DQ-NEXT: vpsubb %ymm1, %ymm0, %ymm1
467467
; AVX512DQ-NEXT: vextracti64x4 $1, %zmm0, %ymm0
468468
; AVX512DQ-NEXT: vpsubb {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
@@ -473,7 +473,7 @@ define <64 x i8> @constant_shift_v64i8_quads(<64 x i8> %a) nounwind {
473473
; AVX512BW: # %bb.0:
474474
; AVX512BW-NEXT: vpsrlvd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm0
475475
; AVX512BW-NEXT: vmovdqa64 {{.*#+}} zmm1 = [16,16,16,16,4,4,4,4,32,32,32,32,1,1,1,1,1,1,1,1,4,4,4,4,1,1,1,1,4,4,4,4,8,8,8,8,16,16,16,16,16,16,16,16,2,2,2,2,64,64,64,64,4,4,4,4,32,32,32,32,128,128,128,128]
476-
; AVX512BW-NEXT: vpternlogq $108, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm1, %zmm0
476+
; AVX512BW-NEXT: vpternlogq {{.*#+}} zmm0 = zmm1 ^ (zmm0 & mem)
477477
; AVX512BW-NEXT: vpsubb %zmm1, %zmm0, %zmm0
478478
; AVX512BW-NEXT: retq
479479
%shift = ashr <64 x i8> %a, <i8 3, i8 3, i8 3, i8 3, i8 5, i8 5, i8 5, i8 5, i8 2, i8 2, i8 2, i8 2, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 5, i8 5, i8 5, i8 5, i8 7, i8 7, i8 7, i8 7, i8 5, i8 5, i8 5, i8 5, i8 4, i8 4, i8 4, i8 4, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 6, i8 6, i8 6, i8 6, i8 1, i8 1, i8 1, i8 1, i8 5, i8 5, i8 5, i8 5, i8 2, i8 2, i8 2, i8 2, i8 0, i8 0, i8 0, i8 0>
@@ -540,7 +540,7 @@ define <64 x i8> @splatconstant_shift_v64i8(<64 x i8> %a) nounwind {
540540
; AVX512BW: # %bb.0:
541541
; AVX512BW-NEXT: vpsrlw $3, %zmm0, %zmm0
542542
; AVX512BW-NEXT: vpbroadcastb {{.*#+}} zmm1 = [16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16]
543-
; AVX512BW-NEXT: vpternlogd $108, {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm1, %zmm0
543+
; AVX512BW-NEXT: vpternlogd {{.*#+}} zmm0 = zmm1 ^ (zmm0 & mem)
544544
; AVX512BW-NEXT: vpsubb %zmm1, %zmm0, %zmm0
545545
; AVX512BW-NEXT: retq
546546
%shift = ashr <64 x i8> %a, <i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3, i8 3>

‎llvm/test/CodeGen/X86/vector-shift-ashr-sub128.ll‎

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -2344,15 +2344,15 @@ define <8 x i8> @splatconstant_shift_v8i8(<8 x i8> %a) nounwind {
23442344
; AVX512DQVL: # %bb.0:
23452345
; AVX512DQVL-NEXT: vpsrlw $3, %xmm0, %xmm0
23462346
; AVX512DQVL-NEXT: vpbroadcastd {{.*#+}} xmm1 = [16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16]
2347-
; AVX512DQVL-NEXT: vpternlogd $108, {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm1, %xmm0
2347+
; AVX512DQVL-NEXT: vpternlogd {{.*#+}} xmm0 = xmm1 ^ (xmm0 & mem)
23482348
; AVX512DQVL-NEXT: vpsubb %xmm1, %xmm0, %xmm0
23492349
; AVX512DQVL-NEXT: retq
23502350
;
23512351
; AVX512BWVL-LABEL: splatconstant_shift_v8i8:
23522352
; AVX512BWVL: # %bb.0:
23532353
; AVX512BWVL-NEXT: vpsrlw $3, %xmm0, %xmm0
23542354
; AVX512BWVL-NEXT: vpbroadcastb {{.*#+}} xmm1 = [16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16]
2355-
; AVX512BWVL-NEXT: vpternlogd $108, {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm1, %xmm0
2355+
; AVX512BWVL-NEXT: vpternlogd {{.*#+}} xmm0 = xmm1 ^ (xmm0 & mem)
23562356
; AVX512BWVL-NEXT: vpsubb %xmm1, %xmm0, %xmm0
23572357
; AVX512BWVL-NEXT: retq
23582358
;
@@ -2414,15 +2414,15 @@ define <4 x i8> @splatconstant_shift_v4i8(<4 x i8> %a) nounwind {
24142414
; AVX512DQVL: # %bb.0:
24152415
; AVX512DQVL-NEXT: vpsrlw $3, %xmm0, %xmm0
24162416
; AVX512DQVL-NEXT: vpbroadcastd {{.*#+}} xmm1 = [16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16]
2417-
; AVX512DQVL-NEXT: vpternlogd $108, {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm1, %xmm0
2417+
; AVX512DQVL-NEXT: vpternlogd {{.*#+}} xmm0 = xmm1 ^ (xmm0 & mem)
24182418
; AVX512DQVL-NEXT: vpsubb %xmm1, %xmm0, %xmm0
24192419
; AVX512DQVL-NEXT: retq
24202420
;
24212421
; AVX512BWVL-LABEL: splatconstant_shift_v4i8:
24222422
; AVX512BWVL: # %bb.0:
24232423
; AVX512BWVL-NEXT: vpsrlw $3, %xmm0, %xmm0
24242424
; AVX512BWVL-NEXT: vpbroadcastb {{.*#+}} xmm1 = [16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16]
2425-
; AVX512BWVL-NEXT: vpternlogd $108, {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm1, %xmm0
2425+
; AVX512BWVL-NEXT: vpternlogd {{.*#+}} xmm0 = xmm1 ^ (xmm0 & mem)
24262426
; AVX512BWVL-NEXT: vpsubb %xmm1, %xmm0, %xmm0
24272427
; AVX512BWVL-NEXT: retq
24282428
;
@@ -2484,15 +2484,15 @@ define <2 x i8> @splatconstant_shift_v2i8(<2 x i8> %a) nounwind {
24842484
; AVX512DQVL: # %bb.0:
24852485
; AVX512DQVL-NEXT: vpsrlw $3, %xmm0, %xmm0
24862486
; AVX512DQVL-NEXT: vpbroadcastd {{.*#+}} xmm1 = [16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16]
2487-
; AVX512DQVL-NEXT: vpternlogd $108, {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm1, %xmm0
2487+
; AVX512DQVL-NEXT: vpternlogd {{.*#+}} xmm0 = xmm1 ^ (xmm0 & mem)
24882488
; AVX512DQVL-NEXT: vpsubb %xmm1, %xmm0, %xmm0
24892489
; AVX512DQVL-NEXT: retq
24902490
;
24912491
; AVX512BWVL-LABEL: splatconstant_shift_v2i8:
24922492
; AVX512BWVL: # %bb.0:
24932493
; AVX512BWVL-NEXT: vpsrlw $3, %xmm0, %xmm0
24942494
; AVX512BWVL-NEXT: vpbroadcastb {{.*#+}} xmm1 = [16,16,16,16,16,16,16,16,16,16,16,16,16,16,16,16]
2495-
; AVX512BWVL-NEXT: vpternlogd $108, {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm1, %xmm0
2495+
; AVX512BWVL-NEXT: vpternlogd {{.*#+}} xmm0 = xmm1 ^ (xmm0 & mem)
24962496
; AVX512BWVL-NEXT: vpsubb %xmm1, %xmm0, %xmm0
24972497
; AVX512BWVL-NEXT: retq
24982498
;

‎llvm/test/CodeGen/X86/vector-shift-shl-256.ll‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1371,7 +1371,7 @@ define <32 x i8> @constant_shift_v32i8(<32 x i8> %a) nounwind {
13711371
; AVX512DQVL-NEXT: vpmaddubsw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm1 # [1,0,4,0,16,0,64,0,128,0,32,0,8,0,2,0,1,0,4,0,16,0,64,0,128,0,32,0,8,0,2,0]
13721372
; AVX512DQVL-NEXT: vpmaddubsw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0 # [0,2,0,8,0,32,0,128,0,64,0,16,0,4,0,1,0,2,0,8,0,32,0,128,0,64,0,16,0,4,0,1]
13731373
; AVX512DQVL-NEXT: vpsllw $8, %ymm0, %ymm0
1374-
; AVX512DQVL-NEXT: vpternlogd $248, {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %ymm1, %ymm0
1374+
; AVX512DQVL-NEXT: vpternlogd {{.*#+}} ymm0 = ymm0 | (ymm1 & mem)
13751375
; AVX512DQVL-NEXT: retq
13761376
;
13771377
; AVX512BWVL-LABEL: constant_shift_v32i8:

‎llvm/test/CodeGen/X86/vector-shift-shl-512.ll‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -324,15 +324,15 @@ define <64 x i8> @constant_shift_v64i8(<64 x i8> %a) nounwind {
324324
; AVX512DQ-NEXT: vpmaddubsw %ymm3, %ymm1, %ymm1
325325
; AVX512DQ-NEXT: vpsllw $8, %ymm1, %ymm1
326326
; AVX512DQ-NEXT: vinserti64x4 $1, %ymm1, %zmm0, %zmm0
327-
; AVX512DQ-NEXT: vpternlogd $248, {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm2, %zmm0
327+
; AVX512DQ-NEXT: vpternlogd {{.*#+}} zmm0 = zmm0 | (zmm2 & mem)
328328
; AVX512DQ-NEXT: retq
329329
;
330330
; AVX512BW-LABEL: constant_shift_v64i8:
331331
; AVX512BW: # %bb.0:
332332
; AVX512BW-NEXT: vpmaddubsw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm1 # [1,0,4,0,16,0,64,0,128,0,32,0,8,0,2,0,1,0,4,0,16,0,64,0,128,0,32,0,8,0,2,0,1,0,4,0,16,0,64,0,128,0,32,0,8,0,2,0,1,0,4,0,16,0,64,0,128,0,32,0,8,0,2,0]
333333
; AVX512BW-NEXT: vpmaddubsw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm0 # [0,2,0,8,0,32,0,128,0,64,0,16,0,4,0,1,0,2,0,8,0,32,0,128,0,64,0,16,0,4,0,1,0,2,0,8,0,32,0,128,0,64,0,16,0,4,0,1,0,2,0,8,0,32,0,128,0,64,0,16,0,4,0,1]
334334
; AVX512BW-NEXT: vpsllw $8, %zmm0, %zmm0
335-
; AVX512BW-NEXT: vpternlogd $248, {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm1, %zmm0
335+
; AVX512BW-NEXT: vpternlogd {{.*#+}} zmm0 = zmm0 | (zmm1 & mem)
336336
; AVX512BW-NEXT: retq
337337
%shift = shl <64 x i8> %a, <i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0, i8 0, i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 7, i8 6, i8 5, i8 4, i8 3, i8 2, i8 1, i8 0>
338338
ret <64 x i8> %shift

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