[RISCV] Use RNE rounding mode for fcvt.s.bf16. Don't print the rounding mode if RNE. (#106948)

topperc · web-flow · commit 2a9f93bf13c7 · 2024-09-03T08:11:05.000-07:00
The rounding mode has no effect on the instruction behavior. Using RNE
matches what we do for fcvt.s.h, fcvt.d.f, fcvt.d.h which are similarily
not affected by the rounding mode.

This appears to match the behavior of binutils. According to compiler
explore, objdump is unable to disassembler fcvt.s.bf16 with a non-zero
rounding mode.
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZfbfmin.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZfbfmin.td
@@ -30,7 +30,7 @@ def riscv_fpround_bf16
 let Predicates = [HasStdExtZfbfmin] in {
 def FCVT_BF16_S : FPUnaryOp_r_frm<0b0100010, 0b01000, FPR16, FPR32, "fcvt.bf16.s">,
                   Sched<[WriteFCvtF32ToF16, ReadFCvtF32ToF16]>;
-def FCVT_S_BF16 : FPUnaryOp_r_frm<0b0100000, 0b00110, FPR32, FPR16, "fcvt.s.bf16">,
+def FCVT_S_BF16 : FPUnaryOp_r_frmlegacy<0b0100000, 0b00110, FPR32, FPR16, "fcvt.s.bf16">,
                   Sched<[WriteFCvtF16ToF32, ReadFCvtF16ToF32]>;
 } // Predicates = [HasStdExtZfbfmin]
 
@@ -50,7 +50,7 @@ def : StPat<store, FSH, FPR16, bf16>;
 def : Pat<(bf16 (riscv_fpround_bf16 FPR32:$rs1)),
           (FCVT_BF16_S FPR32:$rs1, FRM_DYN)>;
 def : Pat<(fpextend (bf16 FPR16:$rs1)),
-          (FCVT_S_BF16 FPR16:$rs1, FRM_DYN)>;
+          (FCVT_S_BF16 FPR16:$rs1, FRM_RNE)>;
 
 // Moves (no conversion)
 def : Pat<(bf16 (riscv_fmv_h_x GPR:$src)), (FMV_H_X GPR:$src)>;
diff --git a/llvm/test/CodeGen/RISCV/bfloat-convert.ll b/llvm/test/CodeGen/RISCV/bfloat-convert.ll
@@ -18,7 +18,7 @@
 define i16 @fcvt_si_bf16(bfloat %a) nounwind {
 ; CHECK32ZFBFMIN-LABEL: fcvt_si_bf16:
 ; CHECK32ZFBFMIN:       # %bb.0:
-; CHECK32ZFBFMIN-NEXT:    fcvt.s.bf16 fa5, fa0, rne
+; CHECK32ZFBFMIN-NEXT:    fcvt.s.bf16 fa5, fa0
 ; CHECK32ZFBFMIN-NEXT:    fcvt.w.s a0, fa5, rtz
 ; CHECK32ZFBFMIN-NEXT:    ret
 ;
@@ -32,7 +32,7 @@ define i16 @fcvt_si_bf16(bfloat %a) nounwind {
 ;
 ; CHECK64ZFBFMIN-LABEL: fcvt_si_bf16:
 ; CHECK64ZFBFMIN:       # %bb.0:
-; CHECK64ZFBFMIN-NEXT:    fcvt.s.bf16 fa5, fa0, rne
+; CHECK64ZFBFMIN-NEXT:    fcvt.s.bf16 fa5, fa0
 ; CHECK64ZFBFMIN-NEXT:    fcvt.l.s a0, fa5, rtz
 ; CHECK64ZFBFMIN-NEXT:    ret
 ;
@@ -120,7 +120,7 @@ declare i16 @llvm.fptosi.sat.i16.bf16(bfloat)
 define i16 @fcvt_ui_bf16(bfloat %a) nounwind {
 ; CHECK32ZFBFMIN-LABEL: fcvt_ui_bf16:
 ; CHECK32ZFBFMIN:       # %bb.0:
-; CHECK32ZFBFMIN-NEXT:    fcvt.s.bf16 fa5, fa0, rne
+; CHECK32ZFBFMIN-NEXT:    fcvt.s.bf16 fa5, fa0
 ; CHECK32ZFBFMIN-NEXT:    fcvt.wu.s a0, fa5, rtz
 ; CHECK32ZFBFMIN-NEXT:    ret
 ;
@@ -134,7 +134,7 @@ define i16 @fcvt_ui_bf16(bfloat %a) nounwind {
 ;
 ; CHECK64ZFBFMIN-LABEL: fcvt_ui_bf16:
 ; CHECK64ZFBFMIN:       # %bb.0:
-; CHECK64ZFBFMIN-NEXT:    fcvt.s.bf16 fa5, fa0, rne
+; CHECK64ZFBFMIN-NEXT:    fcvt.s.bf16 fa5, fa0
 ; CHECK64ZFBFMIN-NEXT:    fcvt.lu.s a0, fa5, rtz
 ; CHECK64ZFBFMIN-NEXT:    ret
 ;
@@ -206,7 +206,7 @@ declare i16 @llvm.fptoui.sat.i16.bf16(bfloat)
 define i32 @fcvt_w_bf16(bfloat %a) nounwind {
 ; CHECK32ZFBFMIN-LABEL: fcvt_w_bf16:
 ; CHECK32ZFBFMIN:       # %bb.0:
-; CHECK32ZFBFMIN-NEXT:    fcvt.s.bf16 fa5, fa0, rne
+; CHECK32ZFBFMIN-NEXT:    fcvt.s.bf16 fa5, fa0
 ; CHECK32ZFBFMIN-NEXT:    fcvt.w.s a0, fa5, rtz
 ; CHECK32ZFBFMIN-NEXT:    ret
 ;
@@ -288,7 +288,7 @@ declare i32 @llvm.fptosi.sat.i32.bf16(bfloat)
 define i32 @fcvt_wu_bf16(bfloat %a) nounwind {
 ; CHECK32ZFBFMIN-LABEL: fcvt_wu_bf16:
 ; CHECK32ZFBFMIN:       # %bb.0:
-; CHECK32ZFBFMIN-NEXT:    fcvt.s.bf16 fa5, fa0, rne
+; CHECK32ZFBFMIN-NEXT:    fcvt.s.bf16 fa5, fa0
 ; CHECK32ZFBFMIN-NEXT:    fcvt.wu.s a0, fa5, rtz
 ; CHECK32ZFBFMIN-NEXT:    ret
 ;
@@ -320,7 +320,7 @@ define i32 @fcvt_wu_bf16(bfloat %a) nounwind {
 define i32 @fcvt_wu_bf16_multiple_use(bfloat %x, ptr %y) nounwind {
 ; CHECK32ZFBFMIN-LABEL: fcvt_wu_bf16_multiple_use:
 ; CHECK32ZFBFMIN:       # %bb.0:
-; CHECK32ZFBFMIN-NEXT:    fcvt.s.bf16 fa5, fa0, rne
+; CHECK32ZFBFMIN-NEXT:    fcvt.s.bf16 fa5, fa0
 ; CHECK32ZFBFMIN-NEXT:    fcvt.wu.s a0, fa5, rtz
 ; CHECK32ZFBFMIN-NEXT:    seqz a1, a0
 ; CHECK32ZFBFMIN-NEXT:    add a0, a0, a1
@@ -438,7 +438,7 @@ define i64 @fcvt_l_bf16(bfloat %a) nounwind {
 ;
 ; CHECK64ZFBFMIN-LABEL: fcvt_l_bf16:
 ; CHECK64ZFBFMIN:       # %bb.0:
-; CHECK64ZFBFMIN-NEXT:    fcvt.s.bf16 fa5, fa0, rne
+; CHECK64ZFBFMIN-NEXT:    fcvt.s.bf16 fa5, fa0
 ; CHECK64ZFBFMIN-NEXT:    fcvt.l.s a0, fa5, rtz
 ; CHECK64ZFBFMIN-NEXT:    ret
 ;
@@ -625,7 +625,7 @@ define i64 @fcvt_lu_bf16(bfloat %a) nounwind {
 ;
 ; CHECK64ZFBFMIN-LABEL: fcvt_lu_bf16:
 ; CHECK64ZFBFMIN:       # %bb.0:
-; CHECK64ZFBFMIN-NEXT:    fcvt.s.bf16 fa5, fa0, rne
+; CHECK64ZFBFMIN-NEXT:    fcvt.s.bf16 fa5, fa0
 ; CHECK64ZFBFMIN-NEXT:    fcvt.lu.s a0, fa5, rtz
 ; CHECK64ZFBFMIN-NEXT:    ret
 ;
@@ -1470,7 +1470,7 @@ define signext i32 @fcvt_bf16_wu_demanded_bits(i32 signext %0, ptr %1) nounwind
 define signext i8 @fcvt_w_s_i8(bfloat %a) nounwind {
 ; CHECK32ZFBFMIN-LABEL: fcvt_w_s_i8:
 ; CHECK32ZFBFMIN:       # %bb.0:
-; CHECK32ZFBFMIN-NEXT:    fcvt.s.bf16 fa5, fa0, rne
+; CHECK32ZFBFMIN-NEXT:    fcvt.s.bf16 fa5, fa0
 ; CHECK32ZFBFMIN-NEXT:    fcvt.w.s a0, fa5, rtz
 ; CHECK32ZFBFMIN-NEXT:    ret
 ;
@@ -1484,7 +1484,7 @@ define signext i8 @fcvt_w_s_i8(bfloat %a) nounwind {
 ;
 ; CHECK64ZFBFMIN-LABEL: fcvt_w_s_i8:
 ; CHECK64ZFBFMIN:       # %bb.0:
-; CHECK64ZFBFMIN-NEXT:    fcvt.s.bf16 fa5, fa0, rne
+; CHECK64ZFBFMIN-NEXT:    fcvt.s.bf16 fa5, fa0
 ; CHECK64ZFBFMIN-NEXT:    fcvt.l.s a0, fa5, rtz
 ; CHECK64ZFBFMIN-NEXT:    ret
 ;
@@ -1572,7 +1572,7 @@ declare i8 @llvm.fptosi.sat.i8.bf16(bfloat)
 define zeroext i8 @fcvt_wu_s_i8(bfloat %a) nounwind {
 ; CHECK32ZFBFMIN-LABEL: fcvt_wu_s_i8:
 ; CHECK32ZFBFMIN:       # %bb.0:
-; CHECK32ZFBFMIN-NEXT:    fcvt.s.bf16 fa5, fa0, rne
+; CHECK32ZFBFMIN-NEXT:    fcvt.s.bf16 fa5, fa0
 ; CHECK32ZFBFMIN-NEXT:    fcvt.wu.s a0, fa5, rtz
 ; CHECK32ZFBFMIN-NEXT:    ret
 ;
@@ -1586,7 +1586,7 @@ define zeroext i8 @fcvt_wu_s_i8(bfloat %a) nounwind {
 ;
 ; CHECK64ZFBFMIN-LABEL: fcvt_wu_s_i8:
 ; CHECK64ZFBFMIN:       # %bb.0:
-; CHECK64ZFBFMIN-NEXT:    fcvt.s.bf16 fa5, fa0, rne
+; CHECK64ZFBFMIN-NEXT:    fcvt.s.bf16 fa5, fa0
 ; CHECK64ZFBFMIN-NEXT:    fcvt.lu.s a0, fa5, rtz
 ; CHECK64ZFBFMIN-NEXT:    ret
 ;
diff --git a/llvm/test/MC/RISCV/fp-default-rounding-mode.s b/llvm/test/MC/RISCV/fp-default-rounding-mode.s
@@ -193,9 +193,12 @@ fcvt.h.lu fa0, a0
 
 # Zfbfmin instructions
 
-# CHECK-INST: fcvt.s.bf16 fa0, fa0, dyn{{$}}
+# CHECK-INST: fcvt.s.bf16 fa0, fa0{{$}}
 # CHECK-ALIAS: fcvt.s.bf16 fa0, fa0{{$}}
 fcvt.s.bf16 fa0, fa0
+# CHECK-INST: fcvt.s.bf16 fa0, fa0{{$}}
+# CHECK-ALIAS: fcvt.s.bf16 fa0, fa0{{$}}
+fcvt.s.bf16 fa0, fa0, rne
 
 # CHECK-INST: fcvt.bf16.s fa0, fa0, dyn{{$}}
 # CHECK-ALIAS: fcvt.bf16.s fa0, fa0{{$}}
diff --git a/llvm/test/MC/RISCV/rv32zfbfmin-valid.s b/llvm/test/MC/RISCV/rv32zfbfmin-valid.s
@@ -49,8 +49,11 @@ fmv.x.h a2, fs7
 fmv.h.x ft1, a6
 
 # CHECK-ASM-AND-OBJ: fcvt.s.bf16 fa0, ft0
-# CHECK-ASM: encoding: [0x53,0x75,0x60,0x40]
+# CHECK-ASM: encoding: [0x53,0x05,0x60,0x40]
 fcvt.s.bf16 fa0, ft0
+# CHECK-ASM-AND-OBJ: fcvt.s.bf16 fa0, ft0, rup
+# CHECK-ASM: encoding: [0x53,0x35,0x60,0x40]
+fcvt.s.bf16 fa0, ft0, rup
 # CHECK-ASM-AND-OBJ: fcvt.bf16.s ft2, fa2
 # CHECK-ASM: encoding: [0x53,0x71,0x86,0x44]
 fcvt.bf16.s ft2, fa2
