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[Codegen] Add a separate stack ID for scalable predicates
This splits out "ScalablePredVector" from the "ScalableVector" StackID this is primarily to allow easy differentiation between vectors and predicates (without inspecting instructions). This new stack ID is not used in many places yet, but will be used in a later patch to mark stack slots that are known to contain predicates.
1 parent dc85d0c commit 2ae8d09

14 files changed

+66
-52
lines changed

‎llvm/include/llvm/CodeGen/MIRYamlMapping.h‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -378,6 +378,7 @@ struct ScalarEnumerationTraits<TargetStackID::Value> {
378378
IO.enumCase(ID, "default", TargetStackID::Default);
379379
IO.enumCase(ID, "sgpr-spill", TargetStackID::SGPRSpill);
380380
IO.enumCase(ID, "scalable-vector", TargetStackID::ScalableVector);
381+
IO.enumCase(ID, "scalable-pred-vector", TargetStackID::ScalablePredVector);
381382
IO.enumCase(ID, "wasm-local", TargetStackID::WasmLocal);
382383
IO.enumCase(ID, "noalloc", TargetStackID::NoAlloc);
383384
}

‎llvm/include/llvm/CodeGen/MachineFrameInfo.h‎

Lines changed: 8 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -494,7 +494,14 @@ class MachineFrameInfo {
494494
/// Should this stack ID be considered in MaxAlignment.
495495
bool contributesToMaxAlignment(uint8_t StackID) {
496496
return StackID == TargetStackID::Default ||
497-
StackID == TargetStackID::ScalableVector;
497+
StackID == TargetStackID::ScalableVector ||
498+
StackID == TargetStackID::ScalablePredVector;
499+
}
500+
501+
bool isScalableStackID(int ObjectIdx) const {
502+
uint8_t StackID = getStackID(ObjectIdx);
503+
return StackID == TargetStackID::ScalableVector ||
504+
StackID == TargetStackID::ScalablePredVector;
498505
}
499506

500507
/// setObjectAlignment - Change the alignment of the specified stack object.

‎llvm/include/llvm/CodeGen/TargetFrameLowering.h‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -32,6 +32,7 @@ enum Value {
3232
SGPRSpill = 1,
3333
ScalableVector = 2,
3434
WasmLocal = 3,
35+
ScalablePredVector = 4,
3536
NoAlloc = 255
3637
};
3738
}

‎llvm/lib/CodeGen/StackFrameLayoutAnalysisPass.cpp‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -72,7 +72,7 @@ struct StackFrameLayoutAnalysis {
7272
: Slot(Idx), Size(MFI.getObjectSize(Idx)),
7373
Align(MFI.getObjectAlign(Idx).value()), Offset(Offset),
7474
SlotTy(Invalid), Scalable(false) {
75-
Scalable = MFI.getStackID(Idx) == TargetStackID::ScalableVector;
75+
Scalable = MFI.isScalableStackID(Idx);
7676
if (MFI.isSpillSlotObjectIndex(Idx))
7777
SlotTy = SlotType::Spill;
7878
else if (MFI.isFixedObjectIndex(Idx))

‎llvm/lib/Target/AArch64/AArch64FrameLowering.cpp‎

Lines changed: 16 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -695,7 +695,7 @@ void AArch64FrameLowering::emitCalleeSavedGPRLocations(
695695
CFIInstBuilder CFIBuilder(MBB, MBBI, MachineInstr::FrameSetup);
696696
for (const auto &Info : CSI) {
697697
unsigned FrameIdx = Info.getFrameIdx();
698-
if (MFI.getStackID(FrameIdx) == TargetStackID::ScalableVector)
698+
if (MFI.isScalableStackID(FrameIdx))
699699
continue;
700700

701701
assert(!Info.isSpilledToReg() && "Spilling to registers not implemented");
@@ -728,7 +728,7 @@ void AArch64FrameLowering::emitCalleeSavedSVELocations(
728728
}
729729

730730
for (const auto &Info : CSI) {
731-
if (MFI.getStackID(Info.getFrameIdx()) != TargetStackID::ScalableVector)
731+
if (!MFI.isScalableStackID(Info.getFrameIdx()))
732732
continue;
733733

734734
// Not all unwinders may know about SVE registers, so assume the lowest
@@ -795,8 +795,7 @@ static void emitCalleeSavedRestores(MachineBasicBlock &MBB,
795795
CFIInstBuilder CFIBuilder(MBB, MBBI, MachineInstr::FrameDestroy);
796796

797797
for (const auto &Info : CSI) {
798-
if (SVE !=
799-
(MFI.getStackID(Info.getFrameIdx()) == TargetStackID::ScalableVector))
798+
if (SVE != MFI.isScalableStackID(Info.getFrameIdx()))
800799
continue;
801800

802801
MCRegister Reg = Info.getReg();
@@ -2898,7 +2897,7 @@ AArch64FrameLowering::getFrameIndexReferenceFromSP(const MachineFunction &MF,
28982897
const auto *AFI = MF.getInfo<AArch64FunctionInfo>();
28992898
bool FPAfterSVECalleeSaves =
29002899
isTargetWindows(MF) && AFI->getSVECalleeSavedStackSize();
2901-
if (MFI.getStackID(FI) == TargetStackID::ScalableVector) {
2900+
if (MFI.isScalableStackID(FI)) {
29022901
if (FPAfterSVECalleeSaves &&
29032902
-ObjectOffset <= (int64_t)AFI->getSVECalleeSavedStackSize())
29042903
return StackOffset::getScalable(ObjectOffset);
@@ -2964,7 +2963,7 @@ StackOffset AArch64FrameLowering::resolveFrameIndexReference(
29642963
const auto &MFI = MF.getFrameInfo();
29652964
int64_t ObjectOffset = MFI.getObjectOffset(FI);
29662965
bool isFixed = MFI.isFixedObjectIndex(FI);
2967-
bool isSVE = MFI.getStackID(FI) == TargetStackID::ScalableVector;
2966+
bool isSVE = MFI.isScalableStackID(FI);
29682967
return resolveFrameOffsetReference(MF, ObjectOffset, isFixed, isSVE, FrameReg,
29692968
PreferFP, ForSimm);
29702969
}
@@ -3687,10 +3686,14 @@ bool AArch64FrameLowering::spillCalleeSavedRegisters(
36873686
}
36883687
// Update the StackIDs of the SVE stack slots.
36893688
MachineFrameInfo &MFI = MF.getFrameInfo();
3690-
if (RPI.Type == RegPairInfo::ZPR || RPI.Type == RegPairInfo::PPR) {
3689+
if (RPI.Type == RegPairInfo::ZPR) {
36913690
MFI.setStackID(FrameIdxReg1, TargetStackID::ScalableVector);
36923691
if (RPI.isPaired())
36933692
MFI.setStackID(FrameIdxReg2, TargetStackID::ScalableVector);
3693+
} else if (RPI.Type == RegPairInfo::PPR) {
3694+
MFI.setStackID(FrameIdxReg1, TargetStackID::ScalablePredVector);
3695+
if (RPI.isPaired())
3696+
MFI.setStackID(FrameIdxReg2, TargetStackID::ScalablePredVector);
36943697
}
36953698
}
36963699
return true;
@@ -3898,8 +3901,7 @@ void AArch64FrameLowering::determineStackHazardSlot(
38983901
for (auto &MI : MBB) {
38993902
std::optional<int> FI = getLdStFrameID(MI, MFI);
39003903
if (FI && *FI >= 0 && *FI < (int)FrameObjects.size()) {
3901-
if (MFI.getStackID(*FI) == TargetStackID::ScalableVector ||
3902-
AArch64InstrInfo::isFpOrNEON(MI))
3904+
if (MFI.isScalableStackID(*FI) || AArch64InstrInfo::isFpOrNEON(MI))
39033905
FrameObjects[*FI] |= 2;
39043906
else
39053907
FrameObjects[*FI] |= 1;
@@ -4344,7 +4346,7 @@ static int64_t determineSVEStackObjectOffsets(MachineFrameInfo &MFI,
43444346
#ifndef NDEBUG
43454347
// First process all fixed stack objects.
43464348
for (int I = MFI.getObjectIndexBegin(); I != 0; ++I)
4347-
assert(MFI.getStackID(I) != TargetStackID::ScalableVector &&
4349+
assert(!MFI.isScalableStackID(I) &&
43484350
"SVE vectors should never be passed on the stack by value, only by "
43494351
"reference.");
43504352
#endif
@@ -4378,12 +4380,11 @@ static int64_t determineSVEStackObjectOffsets(MachineFrameInfo &MFI,
43784380
int StackProtectorFI = -1;
43794381
if (MFI.hasStackProtectorIndex()) {
43804382
StackProtectorFI = MFI.getStackProtectorIndex();
4381-
if (MFI.getStackID(StackProtectorFI) == TargetStackID::ScalableVector)
4383+
if (MFI.isScalableStackID(StackProtectorFI))
43824384
ObjectsToAllocate.push_back(StackProtectorFI);
43834385
}
43844386
for (int I = 0, E = MFI.getObjectIndexEnd(); I != E; ++I) {
4385-
unsigned StackID = MFI.getStackID(I);
4386-
if (StackID != TargetStackID::ScalableVector)
4387+
if (!MFI.isScalableStackID(I))
43874388
continue;
43884389
if (I == StackProtectorFI)
43894390
continue;
@@ -5387,8 +5388,7 @@ void AArch64FrameLowering::orderFrameObjects(
53875388
if (AFI.hasStackHazardSlotIndex()) {
53885389
std::optional<int> FI = getLdStFrameID(MI, MFI);
53895390
if (FI && *FI >= 0 && *FI < (int)FrameObjects.size()) {
5390-
if (MFI.getStackID(*FI) == TargetStackID::ScalableVector ||
5391-
AArch64InstrInfo::isFpOrNEON(MI))
5391+
if (MFI.isScalableStackID(*FI) || AArch64InstrInfo::isFpOrNEON(MI))
53925392
FrameObjects[*FI].Accesses |= FrameObject::AccessFPR;
53935393
else
53945394
FrameObjects[*FI].Accesses |= FrameObject::AccessGPR;
@@ -5746,7 +5746,7 @@ void AArch64FrameLowering::emitRemarks(
57465746
}
57475747

57485748
unsigned RegTy = StackAccess::AccessType::GPR;
5749-
if (MFI.getStackID(FrameIdx) == TargetStackID::ScalableVector) {
5749+
if (MFI.isScalableStackID(FrameIdx)) {
57505750
// SPILL_PPR_TO_ZPR_SLOT_PSEUDO and FILL_PPR_FROM_ZPR_SLOT_PSEUDO
57515751
// spill/fill the predicate as a data vector (so are an FPR access).
57525752
if (MI.getOpcode() != AArch64::SPILL_PPR_TO_ZPR_SLOT_PSEUDO &&

‎llvm/lib/Target/AArch64/AArch64FrameLowering.h‎

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -119,6 +119,7 @@ class AArch64FrameLowering : public TargetFrameLowering {
119119
return false;
120120
case TargetStackID::Default:
121121
case TargetStackID::ScalableVector:
122+
case TargetStackID::ScalablePredVector:
122123
case TargetStackID::NoAlloc:
123124
return true;
124125
}
@@ -127,7 +128,8 @@ class AArch64FrameLowering : public TargetFrameLowering {
127128
bool isStackIdSafeForLocalArea(unsigned StackId) const override {
128129
// We don't support putting SVE objects into the pre-allocated local
129130
// frame block at the moment.
130-
return StackId != TargetStackID::ScalableVector;
131+
return (StackId != TargetStackID::ScalableVector &&
132+
StackId != TargetStackID::ScalablePredVector);
131133
}
132134

133135
void

‎llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -7497,7 +7497,7 @@ bool AArch64DAGToDAGISel::SelectAddrModeIndexedSVE(SDNode *Root, SDValue N,
74977497
int FI = cast<FrameIndexSDNode>(N)->getIndex();
74987498
// We can only encode VL scaled offsets, so only fold in frame indexes
74997499
// referencing SVE objects.
7500-
if (MFI.getStackID(FI) == TargetStackID::ScalableVector) {
7500+
if (MFI.isScalableStackID(FI)) {
75017501
Base = CurDAG->getTargetFrameIndex(FI, TLI->getPointerTy(DL));
75027502
OffImm = CurDAG->getTargetConstant(0, SDLoc(N), MVT::i64);
75037503
return true;
@@ -7543,7 +7543,7 @@ bool AArch64DAGToDAGISel::SelectAddrModeIndexedSVE(SDNode *Root, SDValue N,
75437543
int FI = cast<FrameIndexSDNode>(Base)->getIndex();
75447544
// We can only encode VL scaled offsets, so only fold in frame indexes
75457545
// referencing SVE objects.
7546-
if (MFI.getStackID(FI) == TargetStackID::ScalableVector)
7546+
if (MFI.isScalableStackID(FI))
75477547
Base = CurDAG->getTargetFrameIndex(FI, TLI->getPointerTy(DL));
75487548
}
75497549

‎llvm/lib/Target/AArch64/AArch64ISelLowering.cpp‎

Lines changed: 8 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -9083,8 +9083,7 @@ void AArch64TargetLowering::AdjustInstrPostInstrSelection(MachineInstr &MI,
90839083
(MI.getOpcode() == AArch64::ADDXri ||
90849084
MI.getOpcode() == AArch64::SUBXri)) {
90859085
const MachineOperand &MO = MI.getOperand(1);
9086-
if (MO.isFI() && MF.getFrameInfo().getStackID(MO.getIndex()) ==
9087-
TargetStackID::ScalableVector)
9086+
if (MO.isFI() && MF.getFrameInfo().isScalableStackID(MO.getIndex()))
90889087
MI.addOperand(MachineOperand::CreateReg(AArch64::VG, /*IsDef=*/false,
90899088
/*IsImplicit=*/true));
90909089
}
@@ -9532,8 +9531,12 @@ AArch64TargetLowering::LowerCall(CallLoweringInfo &CLI,
95329531
Align Alignment = DAG.getDataLayout().getPrefTypeAlign(Ty);
95339532
MachineFrameInfo &MFI = MF.getFrameInfo();
95349533
int FI = MFI.CreateStackObject(StoreSize, Alignment, false);
9535-
if (isScalable)
9536-
MFI.setStackID(FI, TargetStackID::ScalableVector);
9534+
if (isScalable) {
9535+
bool IsPred = VA.getValVT() == MVT::aarch64svcount ||
9536+
VA.getValVT().getVectorElementType() == MVT::i1;
9537+
MFI.setStackID(FI, IsPred ? TargetStackID::ScalablePredVector
9538+
: TargetStackID::ScalableVector);
9539+
}
95379540

95389541
MachinePointerInfo MPI = MachinePointerInfo::getFixedStack(MF, FI);
95399542
SDValue Ptr = DAG.getFrameIndex(
@@ -29287,7 +29290,7 @@ void AArch64TargetLowering::finalizeLowering(MachineFunction &MF) const {
2928729290
// than doing it here in finalizeLowering.
2928829291
if (MFI.hasStackProtectorIndex()) {
2928929292
for (unsigned int i = 0, e = MFI.getObjectIndexEnd(); i != e; ++i) {
29290-
if (MFI.getStackID(i) == TargetStackID::ScalableVector &&
29293+
if (MFI.isScalableStackID(i) &&
2929129294
MFI.getObjectSSPLayout(i) != MachineFrameInfo::SSPLK_None) {
2929229295
MFI.setStackID(MFI.getStackProtectorIndex(),
2929329296
TargetStackID::ScalableVector);

‎llvm/lib/Target/AArch64/AArch64InstrInfo.cpp‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -5572,7 +5572,7 @@ void AArch64InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
55725572
assert(Subtarget.isSVEorStreamingSVEAvailable() &&
55735573
"Unexpected register store without SVE store instructions");
55745574
Opc = AArch64::STR_PXI;
5575-
StackID = TargetStackID::ScalableVector;
5575+
StackID = TargetStackID::ScalablePredVector;
55765576
}
55775577
break;
55785578
}
@@ -5587,7 +5587,7 @@ void AArch64InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
55875587
Opc = AArch64::STRSui;
55885588
else if (AArch64::PPR2RegClass.hasSubClassEq(RC)) {
55895589
Opc = AArch64::STR_PPXI;
5590-
StackID = TargetStackID::ScalableVector;
5590+
StackID = TargetStackID::ScalablePredVector;
55915591
}
55925592
break;
55935593
case 8:
@@ -5757,7 +5757,7 @@ void AArch64InstrInfo::loadRegFromStackSlot(
57575757
if (IsPNR)
57585758
PNRReg = DestReg;
57595759
Opc = AArch64::LDR_PXI;
5760-
StackID = TargetStackID::ScalableVector;
5760+
StackID = TargetStackID::ScalablePredVector;
57615761
}
57625762
break;
57635763
}
@@ -5772,7 +5772,7 @@ void AArch64InstrInfo::loadRegFromStackSlot(
57725772
Opc = AArch64::LDRSui;
57735773
else if (AArch64::PPR2RegClass.hasSubClassEq(RC)) {
57745774
Opc = AArch64::LDR_PPXI;
5775-
StackID = TargetStackID::ScalableVector;
5775+
StackID = TargetStackID::ScalablePredVector;
57765776
}
57775777
break;
57785778
case 8:

‎llvm/test/CodeGen/AArch64/debug-info-sve-dbg-declare.mir‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -164,10 +164,10 @@ stack:
164164
- { id: 1, name: z1.addr, size: 16, alignment: 16, stack-id: scalable-vector,
165165
debug-info-variable: '!31', debug-info-expression: '!DIExpression()',
166166
debug-info-location: '!32' }
167-
- { id: 2, name: p0.addr, size: 2, alignment: 2, stack-id: scalable-vector,
167+
- { id: 2, name: p0.addr, size: 2, alignment: 2, stack-id: scalable-pred-vector,
168168
debug-info-variable: '!33', debug-info-expression: '!DIExpression()',
169169
debug-info-location: '!34' }
170-
- { id: 3, name: p1.addr, size: 2, alignment: 2, stack-id: scalable-vector,
170+
- { id: 3, name: p1.addr, size: 2, alignment: 2, stack-id: scalable-pred-vector,
171171
debug-info-variable: '!35', debug-info-expression: '!DIExpression()',
172172
debug-info-location: '!36' }
173173
- { id: 4, name: w0.addr, size: 4, alignment: 4, local-offset: -4, debug-info-variable: '!37',
@@ -181,10 +181,10 @@ stack:
181181
- { id: 7, name: localv1, size: 16, alignment: 16, stack-id: scalable-vector,
182182
debug-info-variable: '!45', debug-info-expression: '!DIExpression()',
183183
debug-info-location: '!46' }
184-
- { id: 8, name: localp0, size: 2, alignment: 2, stack-id: scalable-vector,
184+
- { id: 8, name: localp0, size: 2, alignment: 2, stack-id: scalable-pred-vector,
185185
debug-info-variable: '!48', debug-info-expression: '!DIExpression()',
186186
debug-info-location: '!49' }
187-
- { id: 9, name: localp1, size: 2, alignment: 2, stack-id: scalable-vector,
187+
- { id: 9, name: localp1, size: 2, alignment: 2, stack-id: scalable-pred-vector,
188188
debug-info-variable: '!51', debug-info-expression: '!DIExpression()',
189189
debug-info-location: '!52' }
190190
machineFunctionInfo: {}

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