@@ -3416,7 +3416,7 @@ void DAGTypeLegalizer::SplitVecRes_PARTIAL_REDUCE_MLA(SDNode *N, SDValue &Lo,
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SDValue Input2 = N->getOperand (2 );
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SDValue AccLo, AccHi;
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- std::tie (AccLo, AccHi) = DAG. SplitVector (Acc, DL );
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+ GetSplitVector (Acc, AccLo, AccHi );
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unsigned Opcode = N->getOpcode ();
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// If the input types don't need splitting, just accumulate into the
@@ -3429,8 +3429,8 @@ void DAGTypeLegalizer::SplitVecRes_PARTIAL_REDUCE_MLA(SDNode *N, SDValue &Lo,
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SDValue Input1Lo, Input1Hi;
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SDValue Input2Lo, Input2Hi;
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- std::tie (Input1Lo, Input1Hi) = DAG. SplitVector (Input1, DL );
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- std::tie (Input2Lo, Input2Hi) = DAG. SplitVector (Input2, DL );
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+ GetSplitVector (Input1, Input1Lo, Input1Hi );
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+ GetSplitVector (Input2, Input2Lo, Input2Hi );
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EVT ResultVT = AccLo.getValueType ();
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Lo = DAG.getNode (Opcode, DL, ResultVT, AccLo, Input1Lo, Input2Lo);
@@ -4761,8 +4761,8 @@ SDValue DAGTypeLegalizer::SplitVecOp_PARTIAL_REDUCE_MLA(SDNode *N) {
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SDLoc DL (N);
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SDValue Input1Lo, Input1Hi, Input2Lo, Input2Hi;
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- std::tie (Input1Lo, Input1Hi) = DAG. SplitVector ( N->getOperand (1 ), DL );
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- std::tie (Input2Lo, Input2Hi) = DAG. SplitVector ( N->getOperand (2 ), DL );
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+ GetSplitVector ( N->getOperand (1 ), Input1Lo, Input1Hi );
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+ GetSplitVector ( N->getOperand (2 ), Input2Lo, Input2Hi );
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unsigned Opcode = N->getOpcode ();
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EVT ResultVT = Acc.getValueType ();
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