fixup! Remove redundant extensions

mshockwave · mshockwave · commit 2b1fa14f32a5 · 2025-04-29T10:45:41.000-07:00
diff --git a/llvm/lib/Target/RISCV/RISCVProcessors.td b/llvm/lib/Target/RISCV/RISCVProcessors.td
@@ -370,9 +370,7 @@ def SIFIVE_P870 : RISCVProcessorModel<"sifive-p870", NoSchedModel,
                                       [FeatureStdExtZama16b,
                                        FeatureStdExtZfh,
                                        FeatureStdExtZifencei,
-                                       FeatureStdExtZihintntl,
                                        FeatureStdExtZkr,
-                                       FeatureStdExtZvbb,
                                        FeatureStdExtZvfbfmin,
                                        FeatureStdExtZvfbfwma,
                                        FeatureStdExtZvfh,
