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[LV] Add tests with multiple F(Max|Min)Num reductions w/o fast-math.
Pre-commits extra test coverage for loops with multiple F(Max|Min)Num reductions w/o fast-math-flags for follow-up PR.
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‎llvm/test/Transforms/LoopVectorize/AArch64/fmax-without-fast-math-flags.ll‎

Lines changed: 46 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -113,3 +113,49 @@ loop:
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exit:
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ret float %max.next
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}
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define float @test_fmax_and_fmin(ptr %src.0, ptr %src.1, i64 %n) {
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; CHECK-LABEL: define float @test_fmax_and_fmin(
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; CHECK-SAME: ptr [[SRC_0:%.*]], ptr [[SRC_1:%.*]], i64 [[N:%.*]]) {
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; CHECK-NEXT: [[ENTRY:.*]]:
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; CHECK-NEXT: br label %[[LOOP:.*]]
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; CHECK: [[LOOP]]:
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; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ]
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; CHECK-NEXT: [[MIN:%.*]] = phi float [ 0.000000e+00, %[[ENTRY]] ], [ [[MIN_NEXT:%.*]], %[[LOOP]] ]
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; CHECK-NEXT: [[MAX:%.*]] = phi float [ 0.000000e+00, %[[ENTRY]] ], [ [[MAX_NEXT:%.*]], %[[LOOP]] ]
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; CHECK-NEXT: [[GEP_SRC_0:%.*]] = getelementptr inbounds nuw float, ptr [[SRC_0]], i64 [[IV]]
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; CHECK-NEXT: [[GEP_SRC_1:%.*]] = getelementptr inbounds nuw float, ptr [[SRC_1]], i64 [[IV]]
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; CHECK-NEXT: [[L_0:%.*]] = load float, ptr [[GEP_SRC_0]], align 4
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; CHECK-NEXT: [[L_1:%.*]] = load float, ptr [[GEP_SRC_1]], align 4
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; CHECK-NEXT: [[MAX_NEXT]] = tail call noundef float @llvm.maxnum.f32(float [[MAX]], float [[L_0]])
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; CHECK-NEXT: [[MIN_NEXT]] = tail call noundef float @llvm.minnum.f32(float [[MIN]], float [[L_1]])
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; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
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; CHECK-NEXT: [[EC:%.*]] = icmp eq i64 [[IV_NEXT]], [[N]]
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; CHECK-NEXT: br i1 [[EC]], label %[[EXIT:.*]], label %[[LOOP]]
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; CHECK: [[EXIT]]:
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; CHECK-NEXT: [[MAX_NEXT_LCSSA:%.*]] = phi float [ [[MAX_NEXT]], %[[LOOP]] ]
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; CHECK-NEXT: [[MIN_NEXT_LCSSA:%.*]] = phi float [ [[MIN_NEXT]], %[[LOOP]] ]
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; CHECK-NEXT: [[SUB:%.*]] = fsub float [[MAX_NEXT_LCSSA]], [[MIN_NEXT_LCSSA]]
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; CHECK-NEXT: ret float [[SUB]]
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;
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entry:
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br label %loop
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loop:
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%iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ]
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%min = phi float [ 0.000000e+00, %entry ], [ %min.next, %loop ]
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%max = phi float [ 0.000000e+00, %entry ], [ %max.next, %loop ]
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%gep.src.0 = getelementptr inbounds nuw float, ptr %src.0, i64 %iv
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%gep.src.1 = getelementptr inbounds nuw float, ptr %src.1, i64 %iv
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%l.0 = load float, ptr %gep.src.0, align 4
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%l.1 = load float, ptr %gep.src.1, align 4
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%max.next = tail call noundef float @llvm.maxnum.f32(float %max, float %l.0)
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%min.next = tail call noundef float @llvm.minnum.f32(float %min, float %l.1)
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%iv.next = add nuw nsw i64 %iv, 1
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%ec = icmp eq i64 %iv.next, %n
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br i1 %ec, label %exit, label %loop
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exit:
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%sub = fsub float %max.next, %min.next
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ret float %sub
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}

‎llvm/test/Transforms/LoopVectorize/fmax-without-fast-math-flags-interleave.ll‎

Lines changed: 46 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -113,3 +113,49 @@ loop:
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exit:
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ret float %max.next
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}
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define float @test_fmax_and_fmin(ptr %src.0, ptr %src.1, i64 %n) {
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; CHECK-LABEL: define float @test_fmax_and_fmin(
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; CHECK-SAME: ptr [[SRC_0:%.*]], ptr [[SRC_1:%.*]], i64 [[N:%.*]]) {
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; CHECK-NEXT: [[ENTRY:.*]]:
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; CHECK-NEXT: br label %[[LOOP:.*]]
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; CHECK: [[LOOP]]:
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; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ]
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; CHECK-NEXT: [[MIN:%.*]] = phi float [ 0.000000e+00, %[[ENTRY]] ], [ [[MIN_NEXT:%.*]], %[[LOOP]] ]
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; CHECK-NEXT: [[MAX:%.*]] = phi float [ 0.000000e+00, %[[ENTRY]] ], [ [[MAX_NEXT:%.*]], %[[LOOP]] ]
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; CHECK-NEXT: [[GEP_SRC_0:%.*]] = getelementptr inbounds nuw float, ptr [[SRC_0]], i64 [[IV]]
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; CHECK-NEXT: [[GEP_SRC_1:%.*]] = getelementptr inbounds nuw float, ptr [[SRC_1]], i64 [[IV]]
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; CHECK-NEXT: [[L_0:%.*]] = load float, ptr [[GEP_SRC_0]], align 4
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; CHECK-NEXT: [[L_1:%.*]] = load float, ptr [[GEP_SRC_1]], align 4
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; CHECK-NEXT: [[MAX_NEXT]] = tail call noundef float @llvm.maxnum.f32(float [[MAX]], float [[L_0]])
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; CHECK-NEXT: [[MIN_NEXT]] = tail call noundef float @llvm.minnum.f32(float [[MIN]], float [[L_1]])
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; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
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; CHECK-NEXT: [[EC:%.*]] = icmp eq i64 [[IV_NEXT]], [[N]]
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; CHECK-NEXT: br i1 [[EC]], label %[[EXIT:.*]], label %[[LOOP]]
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; CHECK: [[EXIT]]:
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; CHECK-NEXT: [[MAX_NEXT_LCSSA:%.*]] = phi float [ [[MAX_NEXT]], %[[LOOP]] ]
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; CHECK-NEXT: [[MIN_NEXT_LCSSA:%.*]] = phi float [ [[MIN_NEXT]], %[[LOOP]] ]
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; CHECK-NEXT: [[SUB:%.*]] = fsub float [[MAX_NEXT_LCSSA]], [[MIN_NEXT_LCSSA]]
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; CHECK-NEXT: ret float [[SUB]]
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;
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entry:
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br label %loop
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loop:
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%iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ]
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%min = phi float [ 0.000000e+00, %entry ], [ %min.next, %loop ]
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%max = phi float [ 0.000000e+00, %entry ], [ %max.next, %loop ]
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%gep.src.0 = getelementptr inbounds nuw float, ptr %src.0, i64 %iv
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%gep.src.1 = getelementptr inbounds nuw float, ptr %src.1, i64 %iv
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%l.0 = load float, ptr %gep.src.0, align 4
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%l.1 = load float, ptr %gep.src.1, align 4
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%max.next = tail call noundef float @llvm.maxnum.f32(float %max, float %l.0)
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%min.next = tail call noundef float @llvm.minnum.f32(float %min, float %l.1)
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%iv.next = add nuw nsw i64 %iv, 1
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%ec = icmp eq i64 %iv.next, %n
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br i1 %ec, label %exit, label %loop
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exit:
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%sub = fsub float %max.next, %min.next
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ret float %sub
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}

‎llvm/test/Transforms/LoopVectorize/fmax-without-fast-math-flags.ll‎

Lines changed: 46 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -683,3 +683,49 @@ loop:
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exit:
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ret float %max.next
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}
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define float @test_fmax_and_fmax(ptr %src.0, ptr %src.1, i64 %n) {
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; CHECK-LABEL: define float @test_fmax_and_fmax(
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; CHECK-SAME: ptr [[SRC_0:%.*]], ptr [[SRC_1:%.*]], i64 [[N:%.*]]) {
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; CHECK-NEXT: [[ENTRY:.*]]:
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; CHECK-NEXT: br label %[[LOOP:.*]]
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; CHECK: [[LOOP]]:
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; CHECK-NEXT: [[IV:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ]
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; CHECK-NEXT: [[MIN:%.*]] = phi float [ 0.000000e+00, %[[ENTRY]] ], [ [[MIN_NEXT:%.*]], %[[LOOP]] ]
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; CHECK-NEXT: [[MAX:%.*]] = phi float [ 0.000000e+00, %[[ENTRY]] ], [ [[MAX_NEXT:%.*]], %[[LOOP]] ]
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; CHECK-NEXT: [[GEP_SRC_0:%.*]] = getelementptr inbounds nuw float, ptr [[SRC_0]], i64 [[IV]]
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; CHECK-NEXT: [[GEP_SRC_1:%.*]] = getelementptr inbounds nuw float, ptr [[SRC_1]], i64 [[IV]]
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; CHECK-NEXT: [[L_0:%.*]] = load float, ptr [[GEP_SRC_0]], align 4
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; CHECK-NEXT: [[L_1:%.*]] = load float, ptr [[GEP_SRC_1]], align 4
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; CHECK-NEXT: [[MAX_NEXT]] = tail call noundef float @llvm.maxnum.f32(float [[MAX]], float [[L_0]])
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; CHECK-NEXT: [[MIN_NEXT]] = tail call noundef float @llvm.minnum.f32(float [[MIN]], float [[L_1]])
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; CHECK-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1
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; CHECK-NEXT: [[EC:%.*]] = icmp eq i64 [[IV_NEXT]], [[N]]
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; CHECK-NEXT: br i1 [[EC]], label %[[EXIT:.*]], label %[[LOOP]]
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; CHECK: [[EXIT]]:
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; CHECK-NEXT: [[MAX_NEXT_LCSSA:%.*]] = phi float [ [[MAX_NEXT]], %[[LOOP]] ]
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; CHECK-NEXT: [[MIN_NEXT_LCSSA:%.*]] = phi float [ [[MIN_NEXT]], %[[LOOP]] ]
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; CHECK-NEXT: [[SUB:%.*]] = fsub float [[MAX_NEXT_LCSSA]], [[MIN_NEXT_LCSSA]]
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; CHECK-NEXT: ret float [[SUB]]
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;
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entry:
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br label %loop
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loop:
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%iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ]
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%min = phi float [ 0.000000e+00, %entry ], [ %min.next, %loop ]
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%max = phi float [ 0.000000e+00, %entry ], [ %max.next, %loop ]
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%gep.src.0 = getelementptr inbounds nuw float, ptr %src.0, i64 %iv
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%gep.src.1 = getelementptr inbounds nuw float, ptr %src.1, i64 %iv
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%l.0 = load float, ptr %gep.src.0, align 4
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%l.1 = load float, ptr %gep.src.1, align 4
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%max.next = tail call noundef float @llvm.maxnum.f32(float %max, float %l.0)
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%min.next = tail call noundef float @llvm.minnum.f32(float %min, float %l.1)
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%iv.next = add nuw nsw i64 %iv, 1
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%ec = icmp eq i64 %iv.next, %n
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br i1 %ec, label %exit, label %loop
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exit:
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%sub = fsub float %max.next, %min.next
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ret float %sub
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}

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