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| 1 | +//===----------------------------------------------------------------------===// |
| 2 | +// |
| 3 | +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. |
| 4 | +// See https://llvm.org/LICENSE.txt for license information. |
| 5 | +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception |
| 6 | +// |
| 7 | +//===----------------------------------------------------------------------===// |
| 8 | + |
| 9 | +#include "PassDetail.h" |
| 10 | +#include "mlir/Dialect/Func/IR/FuncOps.h" |
| 11 | +#include "mlir/IR/Block.h" |
| 12 | +#include "mlir/IR/Operation.h" |
| 13 | +#include "mlir/IR/PatternMatch.h" |
| 14 | +#include "mlir/IR/Region.h" |
| 15 | +#include "mlir/Support/LogicalResult.h" |
| 16 | +#include "mlir/Transforms/GreedyPatternRewriteDriver.h" |
| 17 | +#include "clang/CIR/Dialect/IR/CIRDialect.h" |
| 18 | +#include "clang/CIR/Dialect/Passes.h" |
| 19 | +#include "llvm/ADT/SmallVector.h" |
| 20 | + |
| 21 | +using namespace mlir; |
| 22 | +using namespace cir; |
| 23 | + |
| 24 | +//===----------------------------------------------------------------------===// |
| 25 | +// Rewrite patterns |
| 26 | +//===----------------------------------------------------------------------===// |
| 27 | + |
| 28 | +namespace { |
| 29 | + |
| 30 | +/// Simplify suitable ternary operations into select operations. |
| 31 | +/// |
| 32 | +/// For now we only simplify those ternary operations whose true and false |
| 33 | +/// branches directly yield a value or a constant. That is, both of the true and |
| 34 | +/// the false branch must either contain a cir.yield operation as the only |
| 35 | +/// operation in the branch, or contain a cir.const operation followed by a |
| 36 | +/// cir.yield operation that yields the constant value. |
| 37 | +/// |
| 38 | +/// For example, we will simplify the following ternary operation: |
| 39 | +/// |
| 40 | +/// %0 = cir.ternary (%condition, true { |
| 41 | +/// %1 = cir.const ... |
| 42 | +/// cir.yield %1 |
| 43 | +/// } false { |
| 44 | +/// cir.yield %2 |
| 45 | +/// }) |
| 46 | +/// |
| 47 | +/// into the following sequence of operations: |
| 48 | +/// |
| 49 | +/// %1 = cir.const ... |
| 50 | +/// %0 = cir.select if %condition then %1 else %2 |
| 51 | +struct SimplifyTernary final : public OpRewritePattern<TernaryOp> { |
| 52 | + using OpRewritePattern<TernaryOp>::OpRewritePattern; |
| 53 | + |
| 54 | + LogicalResult matchAndRewrite(TernaryOp op, |
| 55 | + PatternRewriter &rewriter) const override { |
| 56 | + if (op->getNumResults() != 1) |
| 57 | + return mlir::failure(); |
| 58 | + |
| 59 | + if (!isSimpleTernaryBranch(op.getTrueRegion()) || |
| 60 | + !isSimpleTernaryBranch(op.getFalseRegion())) |
| 61 | + return mlir::failure(); |
| 62 | + |
| 63 | + cir::YieldOp trueBranchYieldOp = |
| 64 | + mlir::cast<cir::YieldOp>(op.getTrueRegion().front().getTerminator()); |
| 65 | + cir::YieldOp falseBranchYieldOp = |
| 66 | + mlir::cast<cir::YieldOp>(op.getFalseRegion().front().getTerminator()); |
| 67 | + mlir::Value trueValue = trueBranchYieldOp.getArgs()[0]; |
| 68 | + mlir::Value falseValue = falseBranchYieldOp.getArgs()[0]; |
| 69 | + |
| 70 | + rewriter.inlineBlockBefore(&op.getTrueRegion().front(), op); |
| 71 | + rewriter.inlineBlockBefore(&op.getFalseRegion().front(), op); |
| 72 | + rewriter.eraseOp(trueBranchYieldOp); |
| 73 | + rewriter.eraseOp(falseBranchYieldOp); |
| 74 | + rewriter.replaceOpWithNewOp<cir::SelectOp>(op, op.getCond(), trueValue, |
| 75 | + falseValue); |
| 76 | + |
| 77 | + return mlir::success(); |
| 78 | + } |
| 79 | + |
| 80 | +private: |
| 81 | + bool isSimpleTernaryBranch(mlir::Region ®ion) const { |
| 82 | + if (!region.hasOneBlock()) |
| 83 | + return false; |
| 84 | + |
| 85 | + mlir::Block &onlyBlock = region.front(); |
| 86 | + mlir::Block::OpListType &ops = onlyBlock.getOperations(); |
| 87 | + |
| 88 | + // The region/block could only contain at most 2 operations. |
| 89 | + if (ops.size() > 2) |
| 90 | + return false; |
| 91 | + |
| 92 | + if (ops.size() == 1) { |
| 93 | + // The region/block only contain a cir.yield operation. |
| 94 | + return true; |
| 95 | + } |
| 96 | + |
| 97 | + // Check whether the region/block contains a cir.const followed by a |
| 98 | + // cir.yield that yields the value. |
| 99 | + auto yieldOp = mlir::cast<cir::YieldOp>(onlyBlock.getTerminator()); |
| 100 | + auto yieldValueDefOp = mlir::dyn_cast_if_present<cir::ConstantOp>( |
| 101 | + yieldOp.getArgs()[0].getDefiningOp()); |
| 102 | + return yieldValueDefOp && yieldValueDefOp->getBlock() == &onlyBlock; |
| 103 | + } |
| 104 | +}; |
| 105 | + |
| 106 | +struct SimplifySelect : public OpRewritePattern<SelectOp> { |
| 107 | + using OpRewritePattern<SelectOp>::OpRewritePattern; |
| 108 | + |
| 109 | + LogicalResult matchAndRewrite(SelectOp op, |
| 110 | + PatternRewriter &rewriter) const final { |
| 111 | + mlir::Operation *trueValueOp = op.getTrueValue().getDefiningOp(); |
| 112 | + mlir::Operation *falseValueOp = op.getFalseValue().getDefiningOp(); |
| 113 | + auto trueValueConstOp = |
| 114 | + mlir::dyn_cast_if_present<cir::ConstantOp>(trueValueOp); |
| 115 | + auto falseValueConstOp = |
| 116 | + mlir::dyn_cast_if_present<cir::ConstantOp>(falseValueOp); |
| 117 | + if (!trueValueConstOp || !falseValueConstOp) |
| 118 | + return mlir::failure(); |
| 119 | + |
| 120 | + auto trueValue = mlir::dyn_cast<cir::BoolAttr>(trueValueConstOp.getValue()); |
| 121 | + auto falseValue = |
| 122 | + mlir::dyn_cast<cir::BoolAttr>(falseValueConstOp.getValue()); |
| 123 | + if (!trueValue || !falseValue) |
| 124 | + return mlir::failure(); |
| 125 | + |
| 126 | + // cir.select if %0 then #true else #false -> %0 |
| 127 | + if (trueValue.getValue() && !falseValue.getValue()) { |
| 128 | + rewriter.replaceAllUsesWith(op, op.getCondition()); |
| 129 | + rewriter.eraseOp(op); |
| 130 | + return mlir::success(); |
| 131 | + } |
| 132 | + |
| 133 | + // cir.select if %0 then #false else #true -> cir.unary not %0 |
| 134 | + if (!trueValue.getValue() && falseValue.getValue()) { |
| 135 | + rewriter.replaceOpWithNewOp<cir::UnaryOp>(op, cir::UnaryOpKind::Not, |
| 136 | + op.getCondition()); |
| 137 | + return mlir::success(); |
| 138 | + } |
| 139 | + |
| 140 | + return mlir::failure(); |
| 141 | + } |
| 142 | +}; |
| 143 | + |
| 144 | +//===----------------------------------------------------------------------===// |
| 145 | +// CIRSimplifyPass |
| 146 | +//===----------------------------------------------------------------------===// |
| 147 | + |
| 148 | +struct CIRSimplifyPass : public CIRSimplifyBase<CIRSimplifyPass> { |
| 149 | + using CIRSimplifyBase::CIRSimplifyBase; |
| 150 | + |
| 151 | + void runOnOperation() override; |
| 152 | +}; |
| 153 | + |
| 154 | +void populateMergeCleanupPatterns(RewritePatternSet &patterns) { |
| 155 | + // clang-format off |
| 156 | + patterns.add< |
| 157 | + SimplifyTernary, |
| 158 | + SimplifySelect |
| 159 | + >(patterns.getContext()); |
| 160 | + // clang-format on |
| 161 | +} |
| 162 | + |
| 163 | +void CIRSimplifyPass::runOnOperation() { |
| 164 | + // Collect rewrite patterns. |
| 165 | + RewritePatternSet patterns(&getContext()); |
| 166 | + populateMergeCleanupPatterns(patterns); |
| 167 | + |
| 168 | + // Collect operations to apply patterns. |
| 169 | + llvm::SmallVector<Operation *, 16> ops; |
| 170 | + getOperation()->walk([&](Operation *op) { |
| 171 | + if (isa<TernaryOp, SelectOp>(op)) |
| 172 | + ops.push_back(op); |
| 173 | + }); |
| 174 | + |
| 175 | + // Apply patterns. |
| 176 | + if (applyOpPatternsGreedily(ops, std::move(patterns)).failed()) |
| 177 | + signalPassFailure(); |
| 178 | +} |
| 179 | + |
| 180 | +} // namespace |
| 181 | + |
| 182 | +std::unique_ptr<Pass> mlir::createCIRSimplifyPass() { |
| 183 | + return std::make_unique<CIRSimplifyPass>(); |
| 184 | +} |
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