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[RISCV] Set the exact flag on the SRL created for converting vscale to a read of vlenb.
We know that vlenb is a multiple of RVVBytesPerBlock so we aren't shifting out any non-zero bits.
1 parent 2488f26 commit 2b7b12f

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8 files changed

+128
-143
lines changed

8 files changed

+128
-143
lines changed

‎llvm/lib/Target/RISCV/RISCVISelLowering.cpp‎

Lines changed: 4 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -7372,8 +7372,11 @@ SDValue RISCVTargetLowering::LowerOperation(SDValue Op,
73727372
Res = DAG.getNode(ISD::MUL, DL, XLenVT, Res,
73737373
DAG.getConstant(Val / 8, DL, XLenVT));
73747374
} else {
7375+
SDNodeFlags Flags;
7376+
Flags.setExact(true);
73757377
SDValue VScale = DAG.getNode(ISD::SRL, DL, XLenVT, Res,
7376-
DAG.getConstant(3, DL, XLenVT));
7378+
DAG.getConstant(3, DL, XLenVT),
7379+
Flags);
73777380
Res = DAG.getNode(ISD::MUL, DL, XLenVT, VScale,
73787381
DAG.getConstant(Val, DL, XLenVT));
73797382
}

‎llvm/test/CodeGen/RISCV/rvv/extract-subvector.ll‎

Lines changed: 5 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -290,8 +290,7 @@ define <vscale x 2 x i8> @extract_nxv32i8_nxv2i8_6(<vscale x 32 x i8> %vec) {
290290
; CHECK-LABEL: extract_nxv32i8_nxv2i8_6:
291291
; CHECK: # %bb.0:
292292
; CHECK-NEXT: csrr a0, vlenb
293-
; CHECK-NEXT: srli a1, a0, 3
294-
; CHECK-NEXT: slli a1, a1, 1
293+
; CHECK-NEXT: srli a1, a0, 2
295294
; CHECK-NEXT: sub a0, a0, a1
296295
; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, ma
297296
; CHECK-NEXT: vslidedown.vx v8, v8, a0
@@ -314,8 +313,7 @@ define <vscale x 2 x i8> @extract_nxv32i8_nxv2i8_22(<vscale x 32 x i8> %vec) {
314313
; CHECK-LABEL: extract_nxv32i8_nxv2i8_22:
315314
; CHECK: # %bb.0:
316315
; CHECK-NEXT: csrr a0, vlenb
317-
; CHECK-NEXT: srli a1, a0, 3
318-
; CHECK-NEXT: slli a1, a1, 1
316+
; CHECK-NEXT: srli a1, a0, 2
319317
; CHECK-NEXT: sub a0, a0, a1
320318
; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, ma
321319
; CHECK-NEXT: vslidedown.vx v8, v10, a0
@@ -341,9 +339,9 @@ define <vscale x 1 x i8> @extract_nxv4i8_nxv1i8_3(<vscale x 4 x i8> %vec) {
341339
; CHECK-LABEL: extract_nxv4i8_nxv1i8_3:
342340
; CHECK: # %bb.0:
343341
; CHECK-NEXT: csrr a0, vlenb
344-
; CHECK-NEXT: srli a0, a0, 3
345-
; CHECK-NEXT: slli a1, a0, 1
346-
; CHECK-NEXT: add a0, a1, a0
342+
; CHECK-NEXT: srli a1, a0, 3
343+
; CHECK-NEXT: srli a0, a0, 2
344+
; CHECK-NEXT: add a0, a0, a1
347345
; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, ma
348346
; CHECK-NEXT: vslidedown.vx v8, v8, a0
349347
; CHECK-NEXT: ret

‎llvm/test/CodeGen/RISCV/rvv/get_vector_length.ll‎

Lines changed: 12 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -257,9 +257,9 @@ define i32 @vector_length_vf3_i32(i32 zeroext %tc) {
257257
; RV32-LABEL: vector_length_vf3_i32:
258258
; RV32: # %bb.0:
259259
; RV32-NEXT: csrr a1, vlenb
260-
; RV32-NEXT: srli a1, a1, 3
261-
; RV32-NEXT: slli a2, a1, 1
262-
; RV32-NEXT: add a1, a2, a1
260+
; RV32-NEXT: srli a2, a1, 3
261+
; RV32-NEXT: srli a1, a1, 2
262+
; RV32-NEXT: add a1, a1, a2
263263
; RV32-NEXT: bltu a0, a1, .LBB22_2
264264
; RV32-NEXT: # %bb.1:
265265
; RV32-NEXT: mv a0, a1
@@ -270,9 +270,9 @@ define i32 @vector_length_vf3_i32(i32 zeroext %tc) {
270270
; RV64: # %bb.0:
271271
; RV64-NEXT: sext.w a0, a0
272272
; RV64-NEXT: csrr a1, vlenb
273-
; RV64-NEXT: srli a1, a1, 3
274-
; RV64-NEXT: slli a2, a1, 1
275-
; RV64-NEXT: add a1, a2, a1
273+
; RV64-NEXT: srli a2, a1, 3
274+
; RV64-NEXT: srli a1, a1, 2
275+
; RV64-NEXT: add a1, a1, a2
276276
; RV64-NEXT: bltu a0, a1, .LBB22_2
277277
; RV64-NEXT: # %bb.1:
278278
; RV64-NEXT: mv a0, a1
@@ -286,9 +286,9 @@ define i32 @vector_length_vf3_XLen(iXLen zeroext %tc) {
286286
; RV32-LABEL: vector_length_vf3_XLen:
287287
; RV32: # %bb.0:
288288
; RV32-NEXT: csrr a1, vlenb
289-
; RV32-NEXT: srli a1, a1, 3
290-
; RV32-NEXT: slli a2, a1, 1
291-
; RV32-NEXT: add a1, a2, a1
289+
; RV32-NEXT: srli a2, a1, 3
290+
; RV32-NEXT: srli a1, a1, 2
291+
; RV32-NEXT: add a1, a1, a2
292292
; RV32-NEXT: bltu a0, a1, .LBB23_2
293293
; RV32-NEXT: # %bb.1:
294294
; RV32-NEXT: mv a0, a1
@@ -299,9 +299,9 @@ define i32 @vector_length_vf3_XLen(iXLen zeroext %tc) {
299299
; RV64: # %bb.0:
300300
; RV64-NEXT: sext.w a0, a0
301301
; RV64-NEXT: csrr a1, vlenb
302-
; RV64-NEXT: srli a1, a1, 3
303-
; RV64-NEXT: slli a2, a1, 1
304-
; RV64-NEXT: add a1, a2, a1
302+
; RV64-NEXT: srli a2, a1, 3
303+
; RV64-NEXT: srli a1, a1, 2
304+
; RV64-NEXT: add a1, a1, a2
305305
; RV64-NEXT: bltu a0, a1, .LBB23_2
306306
; RV64-NEXT: # %bb.1:
307307
; RV64-NEXT: mv a0, a1

‎llvm/test/CodeGen/RISCV/rvv/legalize-load-sdnode.ll‎

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -8,9 +8,9 @@ define <vscale x 3 x i8> @load_nxv3i8(ptr %ptr) {
88
; CHECK-LABEL: load_nxv3i8:
99
; CHECK: # %bb.0:
1010
; CHECK-NEXT: csrr a1, vlenb
11-
; CHECK-NEXT: srli a1, a1, 3
12-
; CHECK-NEXT: slli a2, a1, 1
13-
; CHECK-NEXT: add a1, a2, a1
11+
; CHECK-NEXT: srli a2, a1, 3
12+
; CHECK-NEXT: srli a1, a1, 2
13+
; CHECK-NEXT: add a1, a1, a2
1414
; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma
1515
; CHECK-NEXT: vle8.v v8, (a0)
1616
; CHECK-NEXT: ret
@@ -22,9 +22,9 @@ define <vscale x 5 x half> @load_nxv5f16(ptr %ptr) {
2222
; CHECK-LABEL: load_nxv5f16:
2323
; CHECK: # %bb.0:
2424
; CHECK-NEXT: csrr a1, vlenb
25-
; CHECK-NEXT: srli a1, a1, 3
26-
; CHECK-NEXT: slli a2, a1, 2
27-
; CHECK-NEXT: add a1, a2, a1
25+
; CHECK-NEXT: srli a2, a1, 3
26+
; CHECK-NEXT: srli a1, a1, 1
27+
; CHECK-NEXT: add a1, a1, a2
2828
; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma
2929
; CHECK-NEXT: vle16.v v8, (a0)
3030
; CHECK-NEXT: ret

‎llvm/test/CodeGen/RISCV/rvv/legalize-store-sdnode.ll‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -8,9 +8,9 @@ define void @store_nxv3i8(<vscale x 3 x i8> %val, ptr %ptr) {
88
; CHECK-LABEL: store_nxv3i8:
99
; CHECK: # %bb.0:
1010
; CHECK-NEXT: csrr a1, vlenb
11-
; CHECK-NEXT: srli a1, a1, 3
12-
; CHECK-NEXT: slli a2, a1, 1
13-
; CHECK-NEXT: add a1, a2, a1
11+
; CHECK-NEXT: srli a2, a1, 3
12+
; CHECK-NEXT: srli a1, a1, 2
13+
; CHECK-NEXT: add a1, a1, a2
1414
; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma
1515
; CHECK-NEXT: vse8.v v8, (a0)
1616
; CHECK-NEXT: ret

‎llvm/test/CodeGen/RISCV/rvv/vandn-sdnode.ll‎

Lines changed: 6 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -2300,10 +2300,9 @@ define void @vand_vx_loop_hoisted_not(ptr %a, i32 noundef signext %mask) {
23002300
; CHECK-RV64-NEXT: li a2, 0
23012301
; CHECK-RV64-NEXT: j .LBB98_5
23022302
; CHECK-RV64-NEXT: .LBB98_2: # %vector.ph
2303-
; CHECK-RV64-NEXT: slli a2, a2, 2
2304-
; CHECK-RV64-NEXT: negw a2, a2
2305-
; CHECK-RV64-NEXT: andi a2, a2, 256
23062303
; CHECK-RV64-NEXT: srli a3, a4, 1
2304+
; CHECK-RV64-NEXT: negw a2, a3
2305+
; CHECK-RV64-NEXT: andi a2, a2, 256
23072306
; CHECK-RV64-NEXT: slli a4, a4, 1
23082307
; CHECK-RV64-NEXT: mv a5, a0
23092308
; CHECK-RV64-NEXT: mv a6, a2
@@ -2395,10 +2394,9 @@ define void @vand_vx_loop_hoisted_not(ptr %a, i32 noundef signext %mask) {
23952394
; CHECK-ZVKB-NOZBB64-NEXT: li a2, 0
23962395
; CHECK-ZVKB-NOZBB64-NEXT: j .LBB98_5
23972396
; CHECK-ZVKB-NOZBB64-NEXT: .LBB98_2: # %vector.ph
2398-
; CHECK-ZVKB-NOZBB64-NEXT: slli a2, a2, 2
2399-
; CHECK-ZVKB-NOZBB64-NEXT: negw a2, a2
2400-
; CHECK-ZVKB-NOZBB64-NEXT: andi a2, a2, 256
24012397
; CHECK-ZVKB-NOZBB64-NEXT: srli a3, a4, 1
2398+
; CHECK-ZVKB-NOZBB64-NEXT: negw a2, a3
2399+
; CHECK-ZVKB-NOZBB64-NEXT: andi a2, a2, 256
24022400
; CHECK-ZVKB-NOZBB64-NEXT: slli a4, a4, 1
24032401
; CHECK-ZVKB-NOZBB64-NEXT: mv a5, a0
24042402
; CHECK-ZVKB-NOZBB64-NEXT: mv a6, a2
@@ -2489,10 +2487,9 @@ define void @vand_vx_loop_hoisted_not(ptr %a, i32 noundef signext %mask) {
24892487
; CHECK-ZVKB-ZBB64-NEXT: li a2, 0
24902488
; CHECK-ZVKB-ZBB64-NEXT: j .LBB98_5
24912489
; CHECK-ZVKB-ZBB64-NEXT: .LBB98_2: # %vector.ph
2492-
; CHECK-ZVKB-ZBB64-NEXT: slli a2, a2, 2
2493-
; CHECK-ZVKB-ZBB64-NEXT: negw a2, a2
2494-
; CHECK-ZVKB-ZBB64-NEXT: andi a2, a2, 256
24952490
; CHECK-ZVKB-ZBB64-NEXT: srli a3, a4, 1
2491+
; CHECK-ZVKB-ZBB64-NEXT: negw a2, a3
2492+
; CHECK-ZVKB-ZBB64-NEXT: andi a2, a2, 256
24962493
; CHECK-ZVKB-ZBB64-NEXT: slli a4, a4, 1
24972494
; CHECK-ZVKB-ZBB64-NEXT: mv a5, a0
24982495
; CHECK-ZVKB-ZBB64-NEXT: mv a6, a2

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