-nosched-above

Author: JonPsson1

llvm/include/llvm/CodeGen/MachineScheduler.h

@@ -241,6 +241,12 @@ class MachineSchedStrategy {
   /// Tell the strategy that MBB is about to be processed.
   virtual void enterMBB(MachineBasicBlock *MBB) {};
 
+  virtual bool disableForRegionPreRA(MachineBasicBlock::iterator begin,
+                                     MachineBasicBlock::iterator end,
+                                     unsigned regioninstrs) const {
+    return false;
+  }
+
   /// Tell the strategy that current MBB is done.
   virtual void leaveMBB() {};
 
@@ -487,6 +493,13 @@ class ScheduleDAGMILive : public ScheduleDAGMI {
                    MachineBasicBlock::iterator end,
                    unsigned regioninstrs) override;
 
+  bool disableForRegion(MachineBasicBlock *bb,
+                        MachineBasicBlock::iterator begin,
+                        MachineBasicBlock::iterator end,
+                        unsigned regioninstrs) const override {
+    return SchedImpl->disableForRegionPreRA(begin, end, regioninstrs);
+  }
+
   /// Implement ScheduleDAGInstrs interface for scheduling a sequence of
   /// reorderable instructions.
   void schedule() override;
@@ -1219,6 +1232,10 @@ class GenericScheduler : public GenericSchedulerBase {
 
   void dumpPolicy() const override;
 
+  bool disableForRegionPreRA(MachineBasicBlock::iterator Begin,
+                             MachineBasicBlock::iterator End,
+                             unsigned NumRegionInstrs) const override;
+
   bool shouldTrackPressure() const override {
     return RegionPolicy.ShouldTrackPressure;
   }

llvm/include/llvm/CodeGen/ScheduleDAGInstrs.h

@@ -319,6 +319,11 @@ namespace llvm {
                              MachineBasicBlock::iterator end,
                              unsigned regioninstrs);
 
+    virtual bool disableForRegion(MachineBasicBlock *bb,
+                                  MachineBasicBlock::iterator begin,
+                                  MachineBasicBlock::iterator end,
+                                  unsigned regioninstrs) const { return false; }
+
     /// Called when the scheduler has finished scheduling the current region.
     virtual void exitRegion();
 

llvm/include/llvm/CodeGen/TargetSubtargetInfo.h

@@ -16,6 +16,7 @@
 #include "llvm/ADT/ArrayRef.h"
 #include "llvm/ADT/SmallVector.h"
 #include "llvm/ADT/StringRef.h"
+#include "llvm/CodeGen/MachineBasicBlock.h"
 #include "llvm/CodeGen/MacroFusion.h"
 #include "llvm/CodeGen/PBQPRAConstraint.h"
 #include "llvm/CodeGen/SchedulerRegistry.h"
@@ -229,6 +230,15 @@ class TargetSubtargetInfo : public MCSubtargetInfo {
   virtual void overrideSchedPolicy(MachineSchedPolicy &Policy,
                                    unsigned NumRegionInstrs) const {}
 
+  /// Allow the subtarget to leave a region untouched. This has purposefully
+  /// been left a bit untangled from other methods as this is hopefully
+  /// just a temporary solution.
+  virtual bool disableForRegionPreRA(MachineBasicBlock::iterator Begin,
+                                     MachineBasicBlock::iterator End,
+                                     unsigned NumRegionInstrs) const {
+    return false;
+  }
+
   // Perform target-specific adjustments to the latency of a schedule
   // dependency.
   // If a pair of operands is associated with the schedule dependency, DefOpIdx

llvm/lib/CodeGen/MachineScheduler.cpp

@@ -641,7 +641,8 @@ void MachineSchedulerBase::scheduleRegions(ScheduleDAGInstrs &Scheduler,
       Scheduler.enterRegion(&*MBB, I, RegionEnd, NumRegionInstrs);
 
       // Skip empty scheduling regions (0 or 1 schedulable instructions).
-      if (I == RegionEnd || I == std::prev(RegionEnd)) {
+      if (I == RegionEnd || I == std::prev(RegionEnd) ||
+          Scheduler.disableForRegion(&*MBB, I, RegionEnd, NumRegionInstrs)) {
         // Close the current region. Bundle the terminator if needed.
         // This invalidates 'RegionEnd' and 'I'.
         Scheduler.exitRegion();
@@ -3334,6 +3335,13 @@ void GenericScheduler::dumpPolicy() const {
 #endif
 }
 
+bool GenericScheduler::disableForRegionPreRA(MachineBasicBlock::iterator Begin,
+                                             MachineBasicBlock::iterator End,
+                                             unsigned NumRegionInstrs) const {
+  const MachineFunction &MF = *Begin->getMF();
+  return MF.getSubtarget().disableForRegionPreRA(Begin, End, NumRegionInstrs);
+}
+
 /// Set IsAcyclicLatencyLimited if the acyclic path is longer than the cyclic
 /// critical path by more cycles than it takes to drain the instruction buffer.
 /// We estimate an upper bounds on in-flight instructions as:

llvm/lib/Target/SystemZ/SystemZSubtarget.cpp

@@ -72,6 +72,22 @@ SystemZSubtarget::SystemZSubtarget(const Triple &TT, const std::string &CPU,
       InstrInfo(initializeSubtargetDependencies(CPU, TuneCPU, FS)),
       TLInfo(TM, *this), FrameLowering(SystemZFrameLowering::create(*this)) {}
 
+
+// EXPERIMENTAL
+cl::opt<unsigned> NoSchedAbove("nosched-above", cl::init(~0U));
+bool SystemZSubtarget::disableForRegionPreRA(MachineBasicBlock::iterator Begin,
+                                             MachineBasicBlock::iterator End,
+                                             unsigned NumRegionInstrs) const {
+  // It seems that the generic scheduler currently can increase spilling heavily
+  // with big / huge regions. Disable it until it is fixed.
+  if (NumRegionInstrs > NoSchedAbove) {
+    LLVM_DEBUG(dbgs() << "Disabling pre-ra mischeduling of region with "
+                      << NumRegionInstrs << " instructions\n";);
+    return true;
+  }
+  return false;
+}
+
 bool SystemZSubtarget::enableSubRegLiveness() const {
   return UseSubRegLiveness;
 }

llvm/lib/Target/SystemZ/SystemZSubtarget.h

@@ -89,6 +89,12 @@ class SystemZSubtarget : public SystemZGenSubtargetInfo {
   // "source" order scheduler.
   bool enableMachineScheduler() const override { return true; }
 
+  // Don't use pre-ra mischeduler for huge regions where it creates a lot of
+  // spilling (temporary solution).
+  bool disableForRegionPreRA(MachineBasicBlock::iterator Begin,
+                             MachineBasicBlock::iterator End,
+                             unsigned NumRegionInstrs) const override;
+
   // This is important for reducing register pressure in vector code.
   bool useAA() const override { return true; }