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[RISCV] Mark pointer masking extensions as non-experimental (#113618)
These extensions were ratified very recently. <https://lf-riscv.atlassian.net/wiki/spaces/HOME/pages/16154732/Ratified+Extensions> I've ensured we have definitions for all extensions in the document <https://drive.google.com/file/d/159QffOTbi3EEbdkKndYRZ2c46D25ZLmO/view?usp=drive_link>. There are no additional CSRs.
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clang/test/Driver/print-supported-extensions-riscv.c

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -120,6 +120,8 @@
120120
// CHECK-NEXT: smcdeleg 1.0 'Smcdeleg' (Counter Delegation Machine Level)
121121
// CHECK-NEXT: smcsrind 1.0 'Smcsrind' (Indirect CSR Access Machine Level)
122122
// CHECK-NEXT: smepmp 1.0 'Smepmp' (Enhanced Physical Memory Protection)
123+
// CHECK-NEXT: smmpm 1.0 'Smmpm' (Machine-level Pointer Masking for M-mode)
124+
// CHECK-NEXT: smnpm 1.0 'Smnpm' (Machine-level Pointer Masking for next lower privilege mode)
123125
// CHECK-NEXT: smrnmi 1.0 'Smrnmi' (Resumable Non-Maskable Interrupts)
124126
// CHECK-NEXT: smstateen 1.0 'Smstateen' (Machine-mode view of the state-enable extension)
125127
// CHECK-NEXT: ssaia 1.0 'Ssaia' (Advanced Interrupt Architecture Supervisor Level)
@@ -128,13 +130,16 @@
128130
// CHECK-NEXT: sscofpmf 1.0 'Sscofpmf' (Count Overflow and Mode-Based Filtering)
129131
// CHECK-NEXT: sscounterenw 1.0 'Sscounterenw' (Support writeable scounteren enable bit for any hpmcounter that is not read-only zero)
130132
// CHECK-NEXT: sscsrind 1.0 'Sscsrind' (Indirect CSR Access Supervisor Level)
133+
// CHECK-NEXT: ssnpm 1.0 'Ssnpm' (Supervisor-level Pointer Masking for next lower privilege mode)
134+
// CHECK-NEXT: sspm 1.0 'Sspm' (Indicates Supervisor-mode Pointer Masking)
131135
// CHECK-NEXT: ssqosid 1.0 'Ssqosid' (Quality-of-Service (QoS) Identifiers)
132136
// CHECK-NEXT: ssstateen 1.0 'Ssstateen' (Supervisor-mode view of the state-enable extension)
133137
// CHECK-NEXT: ssstrict 1.0 'Ssstrict' (No non-conforming extensions are present)
134138
// CHECK-NEXT: sstc 1.0 'Sstc' (Supervisor-mode timer interrupts)
135139
// CHECK-NEXT: sstvala 1.0 'Sstvala' (stval provides all needed values)
136140
// CHECK-NEXT: sstvecd 1.0 'Sstvecd' (stvec supports Direct mode)
137141
// CHECK-NEXT: ssu64xl 1.0 'Ssu64xl' (UXLEN=64 supported)
142+
// CHECK-NEXT: supm 1.0 'Supm' (Indicates User-mode Pointer Masking)
138143
// CHECK-NEXT: svade 1.0 'Svade' (Raise exceptions on improper A/D bits)
139144
// CHECK-NEXT: svadu 1.0 'Svadu' (Hardware A/D updates)
140145
// CHECK-NEXT: svbare 1.0 'Svbare' $(satp mode Bare supported)
@@ -177,12 +182,7 @@
177182
// CHECK-NEXT: zvbc32e 0.7 'Zvbc32e' (Vector Carryless Multiplication with 32-bits elements)
178183
// CHECK-NEXT: zvkgs 0.7 'Zvkgs' (Vector-Scalar GCM instructions for Cryptography)
179184
// CHECK-NEXT: smctr 1.0 'Smctr' (Control Transfer Records Machine Level)
180-
// CHECK-NEXT: smmpm 1.0 'Smmpm' (Machine-level Pointer Masking for M-mode)
181-
// CHECK-NEXT: smnpm 1.0 'Smnpm' (Machine-level Pointer Masking for next lower privilege mode)
182185
// CHECK-NEXT: ssctr 1.0 'Ssctr' (Control Transfer Records Supervisor Level)
183-
// CHECK-NEXT: ssnpm 1.0 'Ssnpm' (Supervisor-level Pointer Masking for next lower privilege mode)
184-
// CHECK-NEXT: sspm 1.0 'Sspm' (Indicates Supervisor-mode Pointer Masking)
185-
// CHECK-NEXT: supm 1.0 'Supm' (Indicates User-mode Pointer Masking)
186186
// CHECK-EMPTY:
187187
// CHECK-NEXT: Supported Profiles
188188
// CHECK-NEXT: rva20s64

clang/test/Driver/riscv-profiles.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -195,7 +195,7 @@
195195
// RVA23S64: "-target-feature" "+ssccptr"
196196
// RVA23S64: "-target-feature" "+sscofpmf"
197197
// RVA23S64: "-target-feature" "+sscounterenw"
198-
// RVA23S64: "-target-feature" "+experimental-ssnpm"
198+
// RVA23S64: "-target-feature" "+ssnpm"
199199
// RVA23S64: "-target-feature" "+ssstateen"
200200
// RVA23S64: "-target-feature" "+sstc"
201201
// RVA23S64: "-target-feature" "+sstvala"

clang/test/Preprocessor/riscv-target-features.c

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -1719,10 +1719,10 @@
17191719
// RUN: -o - | FileCheck --check-prefix=CHECK-ZICFISS-EXT %s
17201720
// CHECK-ZICFISS-EXT: __riscv_zicfiss 1000000{{$}}
17211721

1722-
// RUN: %clang --target=riscv32 -menable-experimental-extensions \
1722+
// RUN: %clang --target=riscv32 \
17231723
// RUN: -march=rv32i_ssnpm1p0 -E -dM %s \
17241724
// RUN: -o - | FileCheck --check-prefix=CHECK-SSNPM-EXT %s
1725-
// RUN: %clang --target=riscv64 -menable-experimental-extensions \
1725+
// RUN: %clang --target=riscv64 \
17261726
// RUN: -march=rv64i_ssnpm1p0 -E -dM %s \
17271727
// RUN: -o - | FileCheck --check-prefix=CHECK-SSNPM-EXT %s
17281728
// CHECK-SSNPM-EXT: __riscv_ssnpm 1000000{{$}}
@@ -1735,26 +1735,26 @@
17351735
// RUN: -o - | FileCheck --check-prefix=CHECK-SMNPM-EXT %s
17361736
// CHECK-SMNPM-EXT: __riscv_smnpm 1000000{{$}}
17371737

1738-
// RUN: %clang --target=riscv32 -menable-experimental-extensions \
1738+
// RUN: %clang --target=riscv32 \
17391739
// RUN: -march=rv32i_smmpm1p0 -E -dM %s \
17401740
// RUN: -o - | FileCheck --check-prefix=CHECK-SMMPM-EXT %s
1741-
// RUN: %clang --target=riscv64 -menable-experimental-extensions \
1741+
// RUN: %clang --target=riscv64 \
17421742
// RUN: -march=rv64i_smmpm1p0 -E -dM %s \
17431743
// RUN: -o - | FileCheck --check-prefix=CHECK-SMMPM-EXT %s
17441744
// CHECK-SMMPM-EXT: __riscv_smmpm 1000000{{$}}
17451745

1746-
// RUN: %clang --target=riscv32 -menable-experimental-extensions \
1746+
// RUN: %clang --target=riscv32 \
17471747
// RUN: -march=rv32i_sspm1p0 -E -dM %s \
17481748
// RUN: -o - | FileCheck --check-prefix=CHECK-SSPM-EXT %s
1749-
// RUN: %clang --target=riscv64 -menable-experimental-extensions \
1749+
// RUN: %clang --target=riscv64 \
17501750
// RUN: -march=rv64i_sspm1p0 -E -dM %s \
17511751
// RUN: -o - | FileCheck --check-prefix=CHECK-SSPM-EXT %s
17521752
// CHECK-SSPM-EXT: __riscv_sspm 1000000{{$}}
17531753

1754-
// RUN: %clang --target=riscv32 -menable-experimental-extensions \
1754+
// RUN: %clang --target=riscv32 \
17551755
// RUN: -march=rv32i_supm1p0 -E -dM %s \
17561756
// RUN: -o - | FileCheck --check-prefix=CHECK-SUPM-EXT %s
1757-
// RUN: %clang --target=riscv64 -menable-experimental-extensions \
1757+
// RUN: %clang --target=riscv64 \
17581758
// RUN: -march=rv64i_supm1p0 -E -dM %s \
17591759
// RUN: -o - | FileCheck --check-prefix=CHECK-SUPM-EXT %s
17601760
// CHECK-SUPM-EXT: __riscv_supm 1000000{{$}}

llvm/docs/RISCVUsage.rst

Lines changed: 5 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -129,6 +129,8 @@ on support follow.
129129
``Smcdeleg`` Supported
130130
``Smcsrind`` Supported
131131
``Smepmp`` Supported
132+
``Smmpm`` Supported
133+
``Smnpm`` Supported
132134
``Smrnmi`` Assembly Support
133135
``Smstateen`` Assembly Support
134136
``Ssaia`` Supported
@@ -137,13 +139,16 @@ on support follow.
137139
``Sscofpmf`` Assembly Support
138140
``Sscounterenw`` Assembly Support (`See note <#riscv-profiles-extensions-note>`__)
139141
``Sscsrind`` Supported
142+
``Ssnpm`` Supported
143+
``Sspm`` Supported
140144
``Ssqosid`` Assembly Support
141145
``Ssstateen`` Assembly Support (`See note <#riscv-profiles-extensions-note>`__)
142146
``Ssstrict`` Assembly Support (`See note <#riscv-profiles-extensions-note>`__)
143147
``Sstc`` Assembly Support
144148
``Sstvala`` Assembly Support (`See note <#riscv-profiles-extensions-note>`__)
145149
``Sstvecd`` Assembly Support (`See note <#riscv-profiles-extensions-note>`__)
146150
``Ssu64xl`` Assembly Support (`See note <#riscv-profiles-extensions-note>`__)
151+
``Supm`` Supported
147152
``Svade`` Assembly Support (`See note <#riscv-profiles-extensions-note>`__)
148153
``Svadu`` Assembly Support
149154
``Svbare`` Assembly Support (`See note <#riscv-profiles-extensions-note>`__)
@@ -308,9 +313,6 @@ LLVM supports (to various degrees) a number of experimental extensions. All exp
308313

309314
The primary goal of experimental support is to assist in the process of ratification by providing an existence proof of an implementation, and simplifying efforts to validate the value of a proposed extension against large code bases. Experimental extensions are expected to either transition to ratified status, or be eventually removed. The decision on whether to accept an experimental extension is currently done on an entirely case by case basis; if you want to propose one, attending the bi-weekly RISC-V sync-up call is strongly advised.
310315

311-
``experimental-ssnpm``, ``experimental-smnpm``, ``experimental-smmpm``, ``experimental-sspm``, ``experimental-supm``
312-
LLVM implements the `v1.0.0-rc2 specification <https://github.com/riscv/riscv-j-extension/releases/tag/pointer-masking-v1.0.0-rc2>`__.
313-
314316
``experimental-zalasr``
315317
LLVM implements the `0.0.5 draft specification <https://github.com/mehnadnerd/riscv-zalasr>`__.
316318

llvm/docs/ReleaseNotes.md

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -171,6 +171,8 @@ Changes to the RISC-V Backend
171171
* Added `Smctr` and `Ssctr` extensions.
172172
* `-mcpu=syntacore-scr7` was added.
173173
* The `Zacas` extension is no longer marked as experimental.
174+
* The `Smmpm`, `Smnpm`, `Ssnpm`, `Supm`, and `Sspm` pointer masking extensions
175+
are no longer marked as experimental.
174176

175177
Changes to the WebAssembly Backend
176178
----------------------------------

llvm/lib/Target/RISCV/RISCVFeatures.td

Lines changed: 10 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -1035,33 +1035,33 @@ def FeatureStdExtSvpbmt
10351035
// privilege mode (U-mode), and for VS- and VU-modes if the H extension is
10361036
// present.
10371037
def FeatureStdExtSsnpm
1038-
: RISCVExperimentalExtension<"ssnpm", 1, 0,
1039-
"'Ssnpm' (Supervisor-level Pointer Masking for next lower privilege mode)">;
1038+
: RISCVExtension<"ssnpm", 1, 0,
1039+
"'Ssnpm' (Supervisor-level Pointer Masking for next lower privilege mode)">;
10401040

10411041
// A machine-level extension that provides pointer masking for the next lower
10421042
// privilege mode (S/HS if S-mode is implemented, or U-mode otherwise).
10431043
def FeatureStdExtSmnpm
1044-
: RISCVExperimentalExtension<"smnpm", 1, 0,
1045-
"'Smnpm' (Machine-level Pointer Masking for next lower privilege mode)">;
1044+
: RISCVExtension<"smnpm", 1, 0,
1045+
"'Smnpm' (Machine-level Pointer Masking for next lower privilege mode)">;
10461046

10471047
// A machine-level extension that provides pointer masking for M-mode.
10481048
def FeatureStdExtSmmpm
1049-
: RISCVExperimentalExtension<"smmpm", 1, 0,
1050-
"'Smmpm' (Machine-level Pointer Masking for M-mode)">;
1049+
: RISCVExtension<"smmpm", 1, 0,
1050+
"'Smmpm' (Machine-level Pointer Masking for M-mode)">;
10511051

10521052
// An extension that indicates that there is pointer-masking support available
10531053
// in supervisor mode, with some facility provided in the supervisor execution
10541054
// environment to control pointer masking.
10551055
def FeatureStdExtSspm
1056-
: RISCVExperimentalExtension<"sspm", 1, 0,
1057-
"'Sspm' (Indicates Supervisor-mode Pointer Masking)">;
1056+
: RISCVExtension<"sspm", 1, 0,
1057+
"'Sspm' (Indicates Supervisor-mode Pointer Masking)">;
10581058

10591059
// An extension that indicates that there is pointer-masking support available
10601060
// in user mode, with some facility provided in the application execution
10611061
// environment to control pointer masking.
10621062
def FeatureStdExtSupm
1063-
: RISCVExperimentalExtension<"supm", 1, 0,
1064-
"'Supm' (Indicates User-mode Pointer Masking)">;
1063+
: RISCVExtension<"supm", 1, 0,
1064+
"'Supm' (Indicates User-mode Pointer Masking)">;
10651065

10661066
def FeatureStdExtSmctr
10671067
: RISCVExperimentalExtension<"smctr", 1, 0,

llvm/test/CodeGen/RISCV/attributes.ll

Lines changed: 10 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -129,11 +129,11 @@
129129
; RUN: llc -mtriple=riscv32 -mattr=+a,+zabha %s -o - | FileCheck --check-prefix=RV32ZABHA %s
130130
; RUN: llc -mtriple=riscv32 -mattr=+zve32x -mattr=+experimental-zvbc32e %s -o - | FileCheck --check-prefix=RV32ZVBC32E %s
131131
; RUN: llc -mtriple=riscv32 -mattr=+zve32x -mattr=+experimental-zvkgs %s -o - | FileCheck --check-prefix=RV32ZVKGS %s
132-
; RUN: llc -mtriple=riscv32 -mattr=+experimental-ssnpm %s -o - | FileCheck --check-prefix=RV32SSNPM %s
133-
; RUN: llc -mtriple=riscv32 -mattr=+experimental-smnpm %s -o - | FileCheck --check-prefix=RV32SMNPM %s
134-
; RUN: llc -mtriple=riscv32 -mattr=+experimental-smmpm %s -o - | FileCheck --check-prefix=RV32SMMPM %s
135-
; RUN: llc -mtriple=riscv32 -mattr=+experimental-sspm %s -o - | FileCheck --check-prefix=RV32SSPM %s
136-
; RUN: llc -mtriple=riscv32 -mattr=+experimental-supm %s -o - | FileCheck --check-prefix=RV32SUPM %s
132+
; RUN: llc -mtriple=riscv32 -mattr=+ssnpm %s -o - | FileCheck --check-prefix=RV32SSNPM %s
133+
; RUN: llc -mtriple=riscv32 -mattr=+smnpm %s -o - | FileCheck --check-prefix=RV32SMNPM %s
134+
; RUN: llc -mtriple=riscv32 -mattr=+smmpm %s -o - | FileCheck --check-prefix=RV32SMMPM %s
135+
; RUN: llc -mtriple=riscv32 -mattr=+sspm %s -o - | FileCheck --check-prefix=RV32SSPM %s
136+
; RUN: llc -mtriple=riscv32 -mattr=+supm %s -o - | FileCheck --check-prefix=RV32SUPM %s
137137
; RUN: llc -mtriple=riscv32 -mattr=+experimental-smctr %s -o - | FileCheck --check-prefix=RV32SMCTR %s
138138
; RUN: llc -mtriple=riscv32 -mattr=+experimental-ssctr %s -o - | FileCheck --check-prefix=RV32SSCTR %s
139139

@@ -272,11 +272,11 @@
272272
; RUN: llc -mtriple=riscv64 -mattr=+a,+zabha %s -o - | FileCheck --check-prefix=RV64ZABHA %s
273273
; RUN: llc -mtriple=riscv64 -mattr=+zve32x -mattr=+experimental-zvbc32e %s -o - | FileCheck --check-prefix=RV64ZVBC32E %s
274274
; RUN: llc -mtriple=riscv64 -mattr=+zve32x -mattr=+experimental-zvkgs %s -o - | FileCheck --check-prefix=RV64ZVKGS %s
275-
; RUN: llc -mtriple=riscv64 -mattr=+experimental-ssnpm %s -o - | FileCheck --check-prefix=RV64SSNPM %s
276-
; RUN: llc -mtriple=riscv64 -mattr=+experimental-smnpm %s -o - | FileCheck --check-prefix=RV64SMNPM %s
277-
; RUN: llc -mtriple=riscv64 -mattr=+experimental-smmpm %s -o - | FileCheck --check-prefix=RV64SMMPM %s
278-
; RUN: llc -mtriple=riscv64 -mattr=+experimental-sspm %s -o - | FileCheck --check-prefix=RV64SSPM %s
279-
; RUN: llc -mtriple=riscv64 -mattr=+experimental-supm %s -o - | FileCheck --check-prefix=RV64SUPM %s
275+
; RUN: llc -mtriple=riscv64 -mattr=+ssnpm %s -o - | FileCheck --check-prefix=RV64SSNPM %s
276+
; RUN: llc -mtriple=riscv64 -mattr=+smnpm %s -o - | FileCheck --check-prefix=RV64SMNPM %s
277+
; RUN: llc -mtriple=riscv64 -mattr=+smmpm %s -o - | FileCheck --check-prefix=RV64SMMPM %s
278+
; RUN: llc -mtriple=riscv64 -mattr=+sspm %s -o - | FileCheck --check-prefix=RV64SSPM %s
279+
; RUN: llc -mtriple=riscv64 -mattr=+supm %s -o - | FileCheck --check-prefix=RV64SUPM %s
280280
; RUN: llc -mtriple=riscv64 -mattr=+experimental-smctr %s -o - | FileCheck --check-prefix=RV64SMCTR %s
281281
; RUN: llc -mtriple=riscv64 -mattr=+experimental-ssctr %s -o - | FileCheck --check-prefix=RV64SSCTR %s
282282

llvm/test/CodeGen/RISCV/rvv/pr107950.ll

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -26,5 +26,5 @@ entry:
2626
; Function Attrs: nocallback nofree nosync nounwind willreturn memory(read)
2727
declare <vscale x 4 x i32> @llvm.masked.gather.nxv4i32.nxv4p0(<vscale x 4 x ptr>, i32 immarg, <vscale x 4 x i1>, <vscale x 4 x i32>) #1
2828

29-
attributes #0 = { "target-features"="+64bit,+d,+f,+relax,+v,+xsifivecdiscarddlone,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b,-a,-b,-c,-e,-experimental-smctr,-experimental-smmpm,-experimental-smnpm,-experimental-ssctr,-experimental-ssnpm,-experimental-sspm,-experimental-supm,-experimental-zacas,-experimental-zalasr,-experimental-zicfilp,-experimental-zicfiss,-experimental-zvbc32e,-experimental-zvkgs,-h,-m,-shcounterenw,-shgatpa,-shtvala,-shvsatpa,-shvstvala,-shvstvecd,-smaia,-smcdeleg,-smcsrind,-smepmp,-smstateen,-ssaia,-ssccfg,-ssccptr,-sscofpmf,-sscounterenw,-sscsrind,-ssqosid,-ssstateen,-ssstrict,-sstc,-sstvala,-sstvecd,-ssu64xl,-svade,-svadu,-svbare,-svinval,-svnapot,-svpbmt,-xcvalu,-xcvbi,-xcvbitmanip,-xcvelw,-xcvmac,-xcvmem,-xcvsimd,-xsfcease,-xsfvcp,-xsfvfnrclipxfqf,-xsfvfwmaccqqq,-xsfvqmaccdod,-xsfvqmaccqoq,-xsifivecflushdlone,-xtheadba,-xtheadbb,-xtheadbs,-xtheadcmo,-xtheadcondmov,-xtheadfmemidx,-xtheadmac,-xtheadmemidx,-xtheadmempair,-xtheadsync,-xtheadvdot,-xventanacondops,-xwchc,-za128rs,-za64rs,-zaamo,-zabha,-zalrsc,-zama16b,-zawrs,-zba,-zbb,-zbc,-zbkb,-zbkc,-zbkx,-zbs,-zca,-zcb,-zcd,-zce,-zcf,-zcmop,-zcmp,-zcmt,-zdinx,-zfa,-zfbfmin,-zfh,-zfhmin,-zfinx,-zhinx,-zhinxmin,-zic64b,-zicbom,-zicbop,-zicboz,-ziccamoa,-ziccif,-zicclsm,-ziccrse,-zicntr,-zicond,-zifencei,-zihintntl,-zihintpause,-zihpm,-zimop,-zk,-zkn,-zknd,-zkne,-zknh,-zkr,-zks,-zksed,-zksh,-zkt,-zmmul,-ztso,-zvbb,-zvbc,-zvfbfmin,-zvfbfwma,-zvfh,-zvfhmin,-zvkb,-zvkg,-zvkn,-zvknc,-zvkned,-zvkng,-zvknha,-zvknhb,-zvks,-zvksc,-zvksed,-zvksg,-zvksh,-zvkt,-zvl1024b,-zvl16384b,-zvl2048b,-zvl256b,-zvl32768b,-zvl4096b,-zvl512b,-zvl65536b,-zvl8192b" }
29+
attributes #0 = { "target-features"="+64bit,+d,+f,+relax,+v,+xsifivecdiscarddlone,+zicsr,+zve32f,+zve32x,+zve64d,+zve64f,+zve64x,+zvl128b,+zvl32b,+zvl64b,-a,-b,-c,-e,-experimental-smctr,-smmpm,-smnpm,-experimental-ssctr,-ssnpm,-sspm,-supm,-experimental-zacas,-experimental-zalasr,-experimental-zicfilp,-experimental-zicfiss,-experimental-zvbc32e,-experimental-zvkgs,-h,-m,-shcounterenw,-shgatpa,-shtvala,-shvsatpa,-shvstvala,-shvstvecd,-smaia,-smcdeleg,-smcsrind,-smepmp,-smstateen,-ssaia,-ssccfg,-ssccptr,-sscofpmf,-sscounterenw,-sscsrind,-ssqosid,-ssstateen,-ssstrict,-sstc,-sstvala,-sstvecd,-ssu64xl,-svade,-svadu,-svbare,-svinval,-svnapot,-svpbmt,-xcvalu,-xcvbi,-xcvbitmanip,-xcvelw,-xcvmac,-xcvmem,-xcvsimd,-xsfcease,-xsfvcp,-xsfvfnrclipxfqf,-xsfvfwmaccqqq,-xsfvqmaccdod,-xsfvqmaccqoq,-xsifivecflushdlone,-xtheadba,-xtheadbb,-xtheadbs,-xtheadcmo,-xtheadcondmov,-xtheadfmemidx,-xtheadmac,-xtheadmemidx,-xtheadmempair,-xtheadsync,-xtheadvdot,-xventanacondops,-xwchc,-za128rs,-za64rs,-zaamo,-zabha,-zalrsc,-zama16b,-zawrs,-zba,-zbb,-zbc,-zbkb,-zbkc,-zbkx,-zbs,-zca,-zcb,-zcd,-zce,-zcf,-zcmop,-zcmp,-zcmt,-zdinx,-zfa,-zfbfmin,-zfh,-zfhmin,-zfinx,-zhinx,-zhinxmin,-zic64b,-zicbom,-zicbop,-zicboz,-ziccamoa,-ziccif,-zicclsm,-ziccrse,-zicntr,-zicond,-zifencei,-zihintntl,-zihintpause,-zihpm,-zimop,-zk,-zkn,-zknd,-zkne,-zknh,-zkr,-zks,-zksed,-zksh,-zkt,-zmmul,-ztso,-zvbb,-zvbc,-zvfbfmin,-zvfbfwma,-zvfh,-zvfhmin,-zvkb,-zvkg,-zvkn,-zvknc,-zvkned,-zvkng,-zvknha,-zvknhb,-zvks,-zvksc,-zvksed,-zvksg,-zvksh,-zvkt,-zvl1024b,-zvl16384b,-zvl2048b,-zvl256b,-zvl32768b,-zvl4096b,-zvl512b,-zvl65536b,-zvl8192b" }
3030
attributes #1 = { nocallback nofree nosync nounwind willreturn memory(read) }

llvm/unittests/TargetParser/RISCVISAInfoTest.cpp

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -1065,6 +1065,8 @@ R"(All available -march extensions for RISC-V
10651065
smcdeleg 1.0
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smcsrind 1.0
10671067
smepmp 1.0
1068+
smmpm 1.0
1069+
smnpm 1.0
10681070
smrnmi 1.0
10691071
smstateen 1.0
10701072
ssaia 1.0
@@ -1073,13 +1075,16 @@ R"(All available -march extensions for RISC-V
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sscofpmf 1.0
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sscounterenw 1.0
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sscsrind 1.0
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ssnpm 1.0
1079+
sspm 1.0
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ssqosid 1.0
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ssstateen 1.0
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ssstrict 1.0
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sstc 1.0
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sstvala 1.0
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sstvecd 1.0
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ssu64xl 1.0
1087+
supm 1.0
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svade 1.0
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svadu 1.0
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svbare 1.0
@@ -1122,12 +1127,7 @@ Experimental extensions
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zvbc32e 0.7
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zvkgs 0.7
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smctr 1.0
1125-
smmpm 1.0
1126-
smnpm 1.0
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ssctr 1.0
1128-
ssnpm 1.0
1129-
sspm 1.0
1130-
supm 1.0
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Supported Profiles
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rva20s64

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