@@ -781,7 +781,6 @@ updateBranchOpInterface(mlir::OpBuilder &builder,
781781 llvm::SmallVector<mlir::RegionSuccessor> entrySuccessors;
782782 llvm::SmallVector<mlir::Attribute> operands (op->getNumOperands (), nullptr );
783783 branch.getEntrySuccessorRegions (operands, entrySuccessors);
784- mlir::ValueRange results = op->getResults ();
785784
786785 for (mlir::RegionSuccessor &successor : entrySuccessors) {
787786 // Only interested in successor regions that are contained within the op.
@@ -792,8 +791,8 @@ updateBranchOpInterface(mlir::OpBuilder &builder,
792791 branch.getEntrySuccessorOperands (successor);
793792 mlir::ValueRange regionArgs = successor.getSuccessorInputs ();
794793
795- for (auto [forwardedOperand, regionArg, result ] :
796- llvm::zip (forwardedOperands, regionArgs, results )) {
794+ for (auto [forwardedOperand, regionArg] :
795+ llvm::zip (forwardedOperands, regionArgs)) {
797796 Type inputType = regionArg.getType ();
798797 // Only update tensor descriptor types in region args.
799798 if (!isa<xegpu::TensorDescType>(inputType))
@@ -873,14 +872,9 @@ void XeGPULayoutPropagatePass::runOnOperation() {
873872 LayoutInfo layout = analysis.getLayoutInfo (val);
874873 if (!layout.isAssigned ())
875874 return {};
876-
877- SmallVector<int , 2 > laneLayout, laneData;
878- for (auto [layout, data] : llvm::zip_equal (layout.getLayoutAsArrayRef (),
879- layout.getDataAsArrayRef ())) {
880- laneLayout.push_back (static_cast <int >(layout));
881- laneData.push_back (static_cast <int >(data));
882- }
883- return xegpu::LayoutAttr::get (val.getContext (), laneLayout, laneData);
875+ return xegpu::LayoutAttr::get (
876+ val.getContext (), llvm::to_vector_of<int >(layout.getLayoutAsArrayRef ()),
877+ llvm::to_vector_of<int >(layout.getDataAsArrayRef ()));
884878 };
885879
886880 mlir::OpBuilder builder (&getContext ());
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