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[PAC][CodeGen][ELF][AArch64] Support signed TLSDESC
Support the following relocations and assembly operators: - `R_AARCH64_AUTH_TLSDESC_ADR_PAGE21` (`:tlsdesc_auth:` for `adrp`) - `R_AARCH64_AUTH_TLSDESC_LD64_LO12` (`:tlsdesc_auth_lo12:` for `ldr`) - `R_AARCH64_AUTH_TLSDESC_ADD_LO12` (`:tlsdesc_auth_lo12:` for `add`) `TLSDESC_AUTH_CALLSEQ` pseudo-instruction is introduced which is later expanded to actual instruction sequence like the following. ``` adrp x0, :tlsdesc_auth:var ldr x16, [x0, #:tlsdesc_auth_lo12:var] add x0, x0, #:tlsdesc_auth_lo12:var .tlsdesccall var blraa x16, x0 (TPIDR_EL0 offset now in x0) ``` Only SelectionDAG ISel is supported. Tests starting with 'ptrauth-' have corresponding variants w/o this prefix.
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12 files changed

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‎llvm/lib/Target/AArch64/AArch64AsmPrinter.cpp‎

Lines changed: 59 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2603,6 +2603,65 @@ void AArch64AsmPrinter::emitInstruction(const MachineInstr *MI) {
26032603
EmitToStreamer(*OutStreamer, TmpInstSB);
26042604
return;
26052605
}
2606+
case AArch64::TLSDESC_AUTH_CALLSEQ: {
2607+
/// lower this to:
2608+
/// adrp x0, :tlsdesc_auth:var
2609+
/// ldr x16, [x0, #:tlsdesc_auth_lo12:var]
2610+
/// add x0, x0, #:tlsdesc_auth_lo12:var
2611+
/// .tlsdesccall var
2612+
/// blraa x16, x0
2613+
/// (TPIDR_EL0 offset now in x0)
2614+
const MachineOperand &MO_Sym = MI->getOperand(0);
2615+
MachineOperand MO_TLSDESC_LO12(MO_Sym), MO_TLSDESC(MO_Sym);
2616+
MCOperand Sym, SymTLSDescLo12, SymTLSDesc;
2617+
MO_TLSDESC_LO12.setTargetFlags(AArch64II::MO_TLS | AArch64II::MO_PAGEOFF);
2618+
MO_TLSDESC.setTargetFlags(AArch64II::MO_TLS | AArch64II::MO_PAGE);
2619+
MCInstLowering.lowerOperand(MO_Sym, Sym);
2620+
MCInstLowering.lowerOperand(MO_TLSDESC_LO12, SymTLSDescLo12);
2621+
MCInstLowering.lowerOperand(MO_TLSDESC, SymTLSDesc);
2622+
2623+
MCInst Adrp;
2624+
Adrp.setOpcode(AArch64::ADRP);
2625+
Adrp.addOperand(MCOperand::createReg(AArch64::X0));
2626+
Adrp.addOperand(SymTLSDesc);
2627+
EmitToStreamer(*OutStreamer, Adrp);
2628+
2629+
MCInst Ldr;
2630+
Ldr.setOpcode(AArch64::LDRXui);
2631+
Ldr.addOperand(MCOperand::createReg(AArch64::X16));
2632+
Ldr.addOperand(MCOperand::createReg(AArch64::X0));
2633+
Ldr.addOperand(SymTLSDescLo12);
2634+
Ldr.addOperand(MCOperand::createImm(0));
2635+
EmitToStreamer(*OutStreamer, Ldr);
2636+
2637+
MCInst Add;
2638+
Add.setOpcode(AArch64::ADDXri);
2639+
Add.addOperand(MCOperand::createReg(AArch64::X0));
2640+
Add.addOperand(MCOperand::createReg(AArch64::X0));
2641+
Add.addOperand(SymTLSDescLo12);
2642+
Add.addOperand(MCOperand::createImm(AArch64_AM::getShiftValue(0)));
2643+
EmitToStreamer(*OutStreamer, Add);
2644+
2645+
// Emit a relocation-annotation. This expands to no code, but requests
2646+
// the following instruction gets an R_AARCH64_TLSDESC_CALL.
2647+
// TODO: we probably don't need that for AUTH TLSDESC. Emit as for now for
2648+
// consistency with non-AUTH case.
2649+
MCInst TLSDescCall;
2650+
TLSDescCall.setOpcode(AArch64::TLSDESCCALL);
2651+
TLSDescCall.addOperand(Sym);
2652+
EmitToStreamer(*OutStreamer, TLSDescCall);
2653+
#ifndef NDEBUG
2654+
--InstsEmitted; // no code emitted
2655+
#endif
2656+
2657+
MCInst Blraa;
2658+
Blraa.setOpcode(AArch64::BLRAA);
2659+
Blraa.addOperand(MCOperand::createReg(AArch64::X16));
2660+
Blraa.addOperand(MCOperand::createReg(AArch64::X0));
2661+
EmitToStreamer(*OutStreamer, Blraa);
2662+
2663+
return;
2664+
}
26062665
case AArch64::TLSDESC_CALLSEQ: {
26072666
/// lower this to:
26082667
/// adrp x0, :tlsdesc:var

‎llvm/lib/Target/AArch64/AArch64ISelLowering.cpp‎

Lines changed: 13 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -2640,6 +2640,7 @@ const char *AArch64TargetLowering::getTargetNodeName(unsigned Opcode) const {
26402640
MAKE_CASE(AArch64ISD::CSINC)
26412641
MAKE_CASE(AArch64ISD::THREAD_POINTER)
26422642
MAKE_CASE(AArch64ISD::TLSDESC_CALLSEQ)
2643+
MAKE_CASE(AArch64ISD::TLSDESC_AUTH_CALLSEQ)
26432644
MAKE_CASE(AArch64ISD::PROBED_ALLOCA)
26442645
MAKE_CASE(AArch64ISD::ABDS_PRED)
26452646
MAKE_CASE(AArch64ISD::ABDU_PRED)
@@ -9890,8 +9891,11 @@ SDValue AArch64TargetLowering::LowerELFTLSDescCallSeq(SDValue SymAddr,
98909891
SDValue Chain = DAG.getEntryNode();
98919892
SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
98929893

9893-
Chain =
9894-
DAG.getNode(AArch64ISD::TLSDESC_CALLSEQ, DL, NodeTys, {Chain, SymAddr});
9894+
unsigned Opcode =
9895+
DAG.getMachineFunction().getInfo<AArch64FunctionInfo>()->hasELFSignedGOT()
9896+
? AArch64ISD::TLSDESC_AUTH_CALLSEQ
9897+
: AArch64ISD::TLSDESC_CALLSEQ;
9898+
Chain = DAG.getNode(Opcode, DL, NodeTys, {Chain, SymAddr});
98959899
SDValue Glue = Chain.getValue(1);
98969900

98979901
return DAG.getCopyFromReg(Chain, DL, AArch64::X0, PtrVT, Glue);
@@ -9904,7 +9908,13 @@ AArch64TargetLowering::LowerELFGlobalTLSAddress(SDValue Op,
99049908

99059909
const GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
99069910

9907-
TLSModel::Model Model = getTargetMachine().getTLSModel(GA->getGlobal());
9911+
TLSModel::Model Model;
9912+
if (DAG.getMachineFunction()
9913+
.getInfo<AArch64FunctionInfo>()
9914+
->hasELFSignedGOT())
9915+
Model = TLSModel::GeneralDynamic;
9916+
else
9917+
Model = getTargetMachine().getTLSModel(GA->getGlobal());
99089918

99099919
if (!EnableAArch64ELFLocalDynamicTLSGeneration) {
99109920
if (Model == TLSModel::LocalDynamic)

‎llvm/lib/Target/AArch64/AArch64ISelLowering.h‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -83,6 +83,7 @@ enum NodeType : unsigned {
8383
// Produces the full sequence of instructions for getting the thread pointer
8484
// offset of a variable into X0, using the TLSDesc model.
8585
TLSDESC_CALLSEQ,
86+
TLSDESC_AUTH_CALLSEQ,
8687
ADRP, // Page address of a TargetGlobalAddress operand.
8788
ADR, // ADR
8889
ADDlow, // Add the low 12 bits of a TargetGlobalAddress operand.

‎llvm/lib/Target/AArch64/AArch64InstrInfo.td‎

Lines changed: 14 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -498,6 +498,8 @@ def SDT_AArch64stnp : SDTypeProfile<0, 3, [SDTCisVT<0, v4i32>, SDTCisSameAs<0, 1
498498
// number of operands (the variable)
499499
def SDT_AArch64TLSDescCallSeq : SDTypeProfile<0,1,
500500
[SDTCisPtrTy<0>]>;
501+
def SDT_AArch64TLSDescAuthCallSeq : SDTypeProfile<0,1,
502+
[SDTCisPtrTy<0>]>;
501503

502504
def SDT_AArch64WrapperLarge : SDTypeProfile<1, 4,
503505
[SDTCisVT<0, i64>, SDTCisVT<1, i32>,
@@ -884,6 +886,10 @@ def AArch64tlsdesc_callseq : SDNode<"AArch64ISD::TLSDESC_CALLSEQ",
884886
[SDNPInGlue, SDNPOutGlue, SDNPHasChain,
885887
SDNPVariadic]>;
886888

889+
def AArch64tlsdesc_auth_callseq : SDNode<"AArch64ISD::TLSDESC_AUTH_CALLSEQ",
890+
SDT_AArch64TLSDescAuthCallSeq,
891+
[SDNPInGlue, SDNPOutGlue, SDNPHasChain,
892+
SDNPVariadic]>;
887893

888894
def AArch64WrapperLarge : SDNode<"AArch64ISD::WrapperLarge",
889895
SDT_AArch64WrapperLarge>;
@@ -3299,8 +3305,16 @@ def TLSDESC_CALLSEQ
32993305
: Pseudo<(outs), (ins i64imm:$sym),
33003306
[(AArch64tlsdesc_callseq tglobaltlsaddr:$sym)]>,
33013307
Sched<[WriteI, WriteLD, WriteI, WriteBrReg]>;
3308+
let isCall = 1, Defs = [NZCV, LR, X0, X16], hasSideEffects = 1, Size = 16,
3309+
isCodeGenOnly = 1 in
3310+
def TLSDESC_AUTH_CALLSEQ
3311+
: Pseudo<(outs), (ins i64imm:$sym),
3312+
[(AArch64tlsdesc_auth_callseq tglobaltlsaddr:$sym)]>,
3313+
Sched<[WriteI, WriteLD, WriteI, WriteBrReg]>;
33023314
def : Pat<(AArch64tlsdesc_callseq texternalsym:$sym),
33033315
(TLSDESC_CALLSEQ texternalsym:$sym)>;
3316+
def : Pat<(AArch64tlsdesc_auth_callseq texternalsym:$sym),
3317+
(TLSDESC_AUTH_CALLSEQ texternalsym:$sym)>;
33043318

33053319
//===----------------------------------------------------------------------===//
33063320
// Conditional branch (immediate) instruction.

‎llvm/lib/Target/AArch64/AArch64MCInstLower.cpp‎

Lines changed: 19 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -194,12 +194,16 @@ MCOperand AArch64MCInstLower::lowerSymbolOperandELF(const MachineOperand &MO,
194194
} else if (MO.getTargetFlags() & AArch64II::MO_TLS) {
195195
TLSModel::Model Model;
196196
if (MO.isGlobal()) {
197-
const GlobalValue *GV = MO.getGlobal();
198-
Model = Printer.TM.getTLSModel(GV);
199-
if (!EnableAArch64ELFLocalDynamicTLSGeneration &&
200-
Model == TLSModel::LocalDynamic)
197+
const MachineFunction *MF = MO.getParent()->getParent()->getParent();
198+
if (MF->getInfo<AArch64FunctionInfo>()->hasELFSignedGOT()) {
201199
Model = TLSModel::GeneralDynamic;
202-
200+
} else {
201+
const GlobalValue *GV = MO.getGlobal();
202+
Model = Printer.TM.getTLSModel(GV);
203+
if (!EnableAArch64ELFLocalDynamicTLSGeneration &&
204+
Model == TLSModel::LocalDynamic)
205+
Model = TLSModel::GeneralDynamic;
206+
}
203207
} else {
204208
assert(MO.isSymbol() &&
205209
StringRef(MO.getSymbolName()) == "_TLS_MODULE_BASE_" &&
@@ -218,10 +222,18 @@ MCOperand AArch64MCInstLower::lowerSymbolOperandELF(const MachineOperand &MO,
218222
case TLSModel::LocalDynamic:
219223
RefFlags |= AArch64MCExpr::VK_DTPREL;
220224
break;
221-
case TLSModel::GeneralDynamic:
222-
RefFlags |= AArch64MCExpr::VK_TLSDESC;
225+
case TLSModel::GeneralDynamic: {
226+
// TODO: it's probably better to introduce MO_TLS_AUTH or smth and avoid
227+
// running hasELFSignedGOT() every time, but existing flags already
228+
// cover all 12 bits of SubReg_TargetFlags field in MachineOperand, and
229+
// making the field wider breaks static assertions.
230+
const MachineFunction *MF = MO.getParent()->getParent()->getParent();
231+
RefFlags |= MF->getInfo<AArch64FunctionInfo>()->hasELFSignedGOT()
232+
? AArch64MCExpr::VK_TLSDESC_AUTH
233+
: AArch64MCExpr::VK_TLSDESC;
223234
break;
224235
}
236+
}
225237
} else if (MO.getTargetFlags() & AArch64II::MO_PREL) {
226238
RefFlags |= AArch64MCExpr::VK_PREL;
227239
} else {

‎llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp‎

Lines changed: 58 additions & 51 deletions
Original file line numberDiff line numberDiff line change
@@ -904,6 +904,7 @@ class AArch64Operand : public MCParsedAsmOperand {
904904
ELFRefKind == AArch64MCExpr::VK_TPREL_LO12_NC ||
905905
ELFRefKind == AArch64MCExpr::VK_GOTTPREL_LO12_NC ||
906906
ELFRefKind == AArch64MCExpr::VK_TLSDESC_LO12 ||
907+
ELFRefKind == AArch64MCExpr::VK_TLSDESC_AUTH_LO12 ||
907908
ELFRefKind == AArch64MCExpr::VK_SECREL_LO12 ||
908909
ELFRefKind == AArch64MCExpr::VK_SECREL_HI12 ||
909910
ELFRefKind == AArch64MCExpr::VK_GOT_PAGE_LO15) {
@@ -1021,6 +1022,7 @@ class AArch64Operand : public MCParsedAsmOperand {
10211022
ELFRefKind == AArch64MCExpr::VK_TPREL_LO12 ||
10221023
ELFRefKind == AArch64MCExpr::VK_TPREL_LO12_NC ||
10231024
ELFRefKind == AArch64MCExpr::VK_TLSDESC_LO12 ||
1025+
ELFRefKind == AArch64MCExpr::VK_TLSDESC_AUTH_LO12 ||
10241026
ELFRefKind == AArch64MCExpr::VK_SECREL_HI12 ||
10251027
ELFRefKind == AArch64MCExpr::VK_SECREL_LO12;
10261028
}
@@ -3314,7 +3316,8 @@ ParseStatus AArch64AsmParser::tryParseAdrpLabel(OperandVector &Operands) {
33143316
ELFRefKind != AArch64MCExpr::VK_GOT_AUTH_PAGE &&
33153317
ELFRefKind != AArch64MCExpr::VK_GOT_PAGE_LO15 &&
33163318
ELFRefKind != AArch64MCExpr::VK_GOTTPREL_PAGE &&
3317-
ELFRefKind != AArch64MCExpr::VK_TLSDESC_PAGE) {
3319+
ELFRefKind != AArch64MCExpr::VK_TLSDESC_PAGE &&
3320+
ELFRefKind != AArch64MCExpr::VK_TLSDESC_AUTH_PAGE) {
33183321
// The operand must be an @page or @gotpage qualified symbolref.
33193322
return Error(S, "page or gotpage label reference expected");
33203323
}
@@ -4391,56 +4394,59 @@ bool AArch64AsmParser::parseSymbolicImmVal(const MCExpr *&ImmVal) {
43914394
return TokError("expect relocation specifier in operand after ':'");
43924395

43934396
std::string LowerCase = getTok().getIdentifier().lower();
4394-
RefKind = StringSwitch<AArch64MCExpr::VariantKind>(LowerCase)
4395-
.Case("lo12", AArch64MCExpr::VK_LO12)
4396-
.Case("abs_g3", AArch64MCExpr::VK_ABS_G3)
4397-
.Case("abs_g2", AArch64MCExpr::VK_ABS_G2)
4398-
.Case("abs_g2_s", AArch64MCExpr::VK_ABS_G2_S)
4399-
.Case("abs_g2_nc", AArch64MCExpr::VK_ABS_G2_NC)
4400-
.Case("abs_g1", AArch64MCExpr::VK_ABS_G1)
4401-
.Case("abs_g1_s", AArch64MCExpr::VK_ABS_G1_S)
4402-
.Case("abs_g1_nc", AArch64MCExpr::VK_ABS_G1_NC)
4403-
.Case("abs_g0", AArch64MCExpr::VK_ABS_G0)
4404-
.Case("abs_g0_s", AArch64MCExpr::VK_ABS_G0_S)
4405-
.Case("abs_g0_nc", AArch64MCExpr::VK_ABS_G0_NC)
4406-
.Case("prel_g3", AArch64MCExpr::VK_PREL_G3)
4407-
.Case("prel_g2", AArch64MCExpr::VK_PREL_G2)
4408-
.Case("prel_g2_nc", AArch64MCExpr::VK_PREL_G2_NC)
4409-
.Case("prel_g1", AArch64MCExpr::VK_PREL_G1)
4410-
.Case("prel_g1_nc", AArch64MCExpr::VK_PREL_G1_NC)
4411-
.Case("prel_g0", AArch64MCExpr::VK_PREL_G0)
4412-
.Case("prel_g0_nc", AArch64MCExpr::VK_PREL_G0_NC)
4413-
.Case("dtprel_g2", AArch64MCExpr::VK_DTPREL_G2)
4414-
.Case("dtprel_g1", AArch64MCExpr::VK_DTPREL_G1)
4415-
.Case("dtprel_g1_nc", AArch64MCExpr::VK_DTPREL_G1_NC)
4416-
.Case("dtprel_g0", AArch64MCExpr::VK_DTPREL_G0)
4417-
.Case("dtprel_g0_nc", AArch64MCExpr::VK_DTPREL_G0_NC)
4418-
.Case("dtprel_hi12", AArch64MCExpr::VK_DTPREL_HI12)
4419-
.Case("dtprel_lo12", AArch64MCExpr::VK_DTPREL_LO12)
4420-
.Case("dtprel_lo12_nc", AArch64MCExpr::VK_DTPREL_LO12_NC)
4421-
.Case("pg_hi21_nc", AArch64MCExpr::VK_ABS_PAGE_NC)
4422-
.Case("tprel_g2", AArch64MCExpr::VK_TPREL_G2)
4423-
.Case("tprel_g1", AArch64MCExpr::VK_TPREL_G1)
4424-
.Case("tprel_g1_nc", AArch64MCExpr::VK_TPREL_G1_NC)
4425-
.Case("tprel_g0", AArch64MCExpr::VK_TPREL_G0)
4426-
.Case("tprel_g0_nc", AArch64MCExpr::VK_TPREL_G0_NC)
4427-
.Case("tprel_hi12", AArch64MCExpr::VK_TPREL_HI12)
4428-
.Case("tprel_lo12", AArch64MCExpr::VK_TPREL_LO12)
4429-
.Case("tprel_lo12_nc", AArch64MCExpr::VK_TPREL_LO12_NC)
4430-
.Case("tlsdesc_lo12", AArch64MCExpr::VK_TLSDESC_LO12)
4431-
.Case("got", AArch64MCExpr::VK_GOT_PAGE)
4432-
.Case("gotpage_lo15", AArch64MCExpr::VK_GOT_PAGE_LO15)
4433-
.Case("got_lo12", AArch64MCExpr::VK_GOT_LO12)
4434-
.Case("got_auth", AArch64MCExpr::VK_GOT_AUTH_PAGE)
4435-
.Case("got_auth_lo12", AArch64MCExpr::VK_GOT_AUTH_LO12)
4436-
.Case("gottprel", AArch64MCExpr::VK_GOTTPREL_PAGE)
4437-
.Case("gottprel_lo12", AArch64MCExpr::VK_GOTTPREL_LO12_NC)
4438-
.Case("gottprel_g1", AArch64MCExpr::VK_GOTTPREL_G1)
4439-
.Case("gottprel_g0_nc", AArch64MCExpr::VK_GOTTPREL_G0_NC)
4440-
.Case("tlsdesc", AArch64MCExpr::VK_TLSDESC_PAGE)
4441-
.Case("secrel_lo12", AArch64MCExpr::VK_SECREL_LO12)
4442-
.Case("secrel_hi12", AArch64MCExpr::VK_SECREL_HI12)
4443-
.Default(AArch64MCExpr::VK_INVALID);
4397+
RefKind =
4398+
StringSwitch<AArch64MCExpr::VariantKind>(LowerCase)
4399+
.Case("lo12", AArch64MCExpr::VK_LO12)
4400+
.Case("abs_g3", AArch64MCExpr::VK_ABS_G3)
4401+
.Case("abs_g2", AArch64MCExpr::VK_ABS_G2)
4402+
.Case("abs_g2_s", AArch64MCExpr::VK_ABS_G2_S)
4403+
.Case("abs_g2_nc", AArch64MCExpr::VK_ABS_G2_NC)
4404+
.Case("abs_g1", AArch64MCExpr::VK_ABS_G1)
4405+
.Case("abs_g1_s", AArch64MCExpr::VK_ABS_G1_S)
4406+
.Case("abs_g1_nc", AArch64MCExpr::VK_ABS_G1_NC)
4407+
.Case("abs_g0", AArch64MCExpr::VK_ABS_G0)
4408+
.Case("abs_g0_s", AArch64MCExpr::VK_ABS_G0_S)
4409+
.Case("abs_g0_nc", AArch64MCExpr::VK_ABS_G0_NC)
4410+
.Case("prel_g3", AArch64MCExpr::VK_PREL_G3)
4411+
.Case("prel_g2", AArch64MCExpr::VK_PREL_G2)
4412+
.Case("prel_g2_nc", AArch64MCExpr::VK_PREL_G2_NC)
4413+
.Case("prel_g1", AArch64MCExpr::VK_PREL_G1)
4414+
.Case("prel_g1_nc", AArch64MCExpr::VK_PREL_G1_NC)
4415+
.Case("prel_g0", AArch64MCExpr::VK_PREL_G0)
4416+
.Case("prel_g0_nc", AArch64MCExpr::VK_PREL_G0_NC)
4417+
.Case("dtprel_g2", AArch64MCExpr::VK_DTPREL_G2)
4418+
.Case("dtprel_g1", AArch64MCExpr::VK_DTPREL_G1)
4419+
.Case("dtprel_g1_nc", AArch64MCExpr::VK_DTPREL_G1_NC)
4420+
.Case("dtprel_g0", AArch64MCExpr::VK_DTPREL_G0)
4421+
.Case("dtprel_g0_nc", AArch64MCExpr::VK_DTPREL_G0_NC)
4422+
.Case("dtprel_hi12", AArch64MCExpr::VK_DTPREL_HI12)
4423+
.Case("dtprel_lo12", AArch64MCExpr::VK_DTPREL_LO12)
4424+
.Case("dtprel_lo12_nc", AArch64MCExpr::VK_DTPREL_LO12_NC)
4425+
.Case("pg_hi21_nc", AArch64MCExpr::VK_ABS_PAGE_NC)
4426+
.Case("tprel_g2", AArch64MCExpr::VK_TPREL_G2)
4427+
.Case("tprel_g1", AArch64MCExpr::VK_TPREL_G1)
4428+
.Case("tprel_g1_nc", AArch64MCExpr::VK_TPREL_G1_NC)
4429+
.Case("tprel_g0", AArch64MCExpr::VK_TPREL_G0)
4430+
.Case("tprel_g0_nc", AArch64MCExpr::VK_TPREL_G0_NC)
4431+
.Case("tprel_hi12", AArch64MCExpr::VK_TPREL_HI12)
4432+
.Case("tprel_lo12", AArch64MCExpr::VK_TPREL_LO12)
4433+
.Case("tprel_lo12_nc", AArch64MCExpr::VK_TPREL_LO12_NC)
4434+
.Case("tlsdesc_lo12", AArch64MCExpr::VK_TLSDESC_LO12)
4435+
.Case("tlsdesc_auth_lo12", AArch64MCExpr::VK_TLSDESC_AUTH_LO12)
4436+
.Case("got", AArch64MCExpr::VK_GOT_PAGE)
4437+
.Case("gotpage_lo15", AArch64MCExpr::VK_GOT_PAGE_LO15)
4438+
.Case("got_lo12", AArch64MCExpr::VK_GOT_LO12)
4439+
.Case("got_auth", AArch64MCExpr::VK_GOT_AUTH_PAGE)
4440+
.Case("got_auth_lo12", AArch64MCExpr::VK_GOT_AUTH_LO12)
4441+
.Case("gottprel", AArch64MCExpr::VK_GOTTPREL_PAGE)
4442+
.Case("gottprel_lo12", AArch64MCExpr::VK_GOTTPREL_LO12_NC)
4443+
.Case("gottprel_g1", AArch64MCExpr::VK_GOTTPREL_G1)
4444+
.Case("gottprel_g0_nc", AArch64MCExpr::VK_GOTTPREL_G0_NC)
4445+
.Case("tlsdesc", AArch64MCExpr::VK_TLSDESC_PAGE)
4446+
.Case("tlsdesc_auth", AArch64MCExpr::VK_TLSDESC_AUTH_PAGE)
4447+
.Case("secrel_lo12", AArch64MCExpr::VK_SECREL_LO12)
4448+
.Case("secrel_hi12", AArch64MCExpr::VK_SECREL_HI12)
4449+
.Default(AArch64MCExpr::VK_INVALID);
44444450

44454451
if (RefKind == AArch64MCExpr::VK_INVALID)
44464452
return TokError("expect relocation specifier in operand after ':'");
@@ -5814,6 +5820,7 @@ bool AArch64AsmParser::validateInstruction(MCInst &Inst, SMLoc &IDLoc,
58145820
ELFRefKind == AArch64MCExpr::VK_TPREL_LO12 ||
58155821
ELFRefKind == AArch64MCExpr::VK_TPREL_LO12_NC ||
58165822
ELFRefKind == AArch64MCExpr::VK_TLSDESC_LO12 ||
5823+
ELFRefKind == AArch64MCExpr::VK_TLSDESC_AUTH_LO12 ||
58175824
ELFRefKind == AArch64MCExpr::VK_SECREL_LO12 ||
58185825
ELFRefKind == AArch64MCExpr::VK_SECREL_HI12) &&
58195826
(Inst.getOpcode() == AArch64::ADDXri ||

‎llvm/lib/Target/AArch64/MCTargetDesc/AArch64ELFObjectWriter.cpp‎

Lines changed: 26 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -178,6 +178,15 @@ unsigned AArch64ELFObjectWriter::getRelocType(MCContext &Ctx,
178178
return R_CLS(TLSIE_ADR_GOTTPREL_PAGE21);
179179
if (SymLoc == AArch64MCExpr::VK_TLSDESC && !IsNC)
180180
return R_CLS(TLSDESC_ADR_PAGE21);
181+
if (SymLoc == AArch64MCExpr::VK_TLSDESC_AUTH && !IsNC) {
182+
if (IsILP32) {
183+
Ctx.reportError(Fixup.getLoc(),
184+
"ILP32 ADRP AUTH relocation not supported "
185+
"(LP64 eqv: AUTH_TLSDESC_ADR_PAGE21)");
186+
return ELF::R_AARCH64_NONE;
187+
}
188+
return ELF::R_AARCH64_AUTH_TLSDESC_ADR_PAGE21;
189+
}
181190
Ctx.reportError(Fixup.getLoc(),
182191
"invalid symbol kind for ADRP relocation");
183192
return ELF::R_AARCH64_NONE;
@@ -249,6 +258,15 @@ unsigned AArch64ELFObjectWriter::getRelocType(MCContext &Ctx,
249258
return R_CLS(TLSLE_ADD_TPREL_LO12);
250259
if (RefKind == AArch64MCExpr::VK_TLSDESC_LO12)
251260
return R_CLS(TLSDESC_ADD_LO12);
261+
if (RefKind == AArch64MCExpr::VK_TLSDESC_AUTH_LO12) {
262+
if (IsILP32) {
263+
Ctx.reportError(Fixup.getLoc(),
264+
"ILP32 ADD AUTH relocation not supported "
265+
"(LP64 eqv: AUTH_TLSDESC_ADD_LO12)");
266+
return ELF::R_AARCH64_NONE;
267+
}
268+
return ELF::R_AARCH64_AUTH_TLSDESC_ADD_LO12;
269+
}
252270
if (RefKind == AArch64MCExpr::VK_GOT_AUTH_LO12 && IsNC) {
253271
if (IsILP32) {
254272
Ctx.reportError(Fixup.getLoc(),
@@ -393,6 +411,14 @@ unsigned AArch64ELFObjectWriter::getRelocType(MCContext &Ctx,
393411
"TLSDESC_LD64_LO12)");
394412
return ELF::R_AARCH64_NONE;
395413
}
414+
if (SymLoc == AArch64MCExpr::VK_TLSDESC_AUTH) {
415+
if (!IsILP32)
416+
return ELF::R_AARCH64_AUTH_TLSDESC_LD64_LO12;
417+
Ctx.reportError(Fixup.getLoc(), "ILP32 64-bit load/store AUTH "
418+
"relocation not supported (LP64 eqv: "
419+
"AUTH_TLSDESC_LD64_LO12)");
420+
return ELF::R_AARCH64_NONE;
421+
}
396422
Ctx.reportError(Fixup.getLoc(),
397423
"invalid fixup for 64-bit load/store instruction");
398424
return ELF::R_AARCH64_NONE;

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